Updating processor microcode

Patent metadata

Field	Value
Publication number	US-10055593-B2
Application number	US-201615056826-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Feb 13, 2013
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

Approaches are described for updating code and/or instructions in one or more computing devices. In particular, various embodiments provide approaches for updating the microcode of one or more processors of a computing device without requiring a restart of the computing device and without disrupting the various components (e.g., applications, virtual machines, etc.) executing on the computing device. The microcode updates can be performed on host computing devices deployed in a resource center of a service provider (e.g., cloud computing service provider), where each host computing device may be executing a hypervisor hosting multiple guest virtual machines (or other guest applications) for the customers of the service provider.

First claim

What is claimed is:

1. A computer implemented method for updating processor microcode, comprising:
receiving, to a host computing device, a microcode patch for a processor of the host computing device, the host computing device including a hypervisor hosting a virtual machine, the microcode patch signed using a private key;
detecting a system management interrupt on the host computing device;
entering a system management mode (SMM) on the host computing device and suspending active program execution of all physical cores in the processor except for a single physical core in the processor;
attempting, by the single physical core executing SMM code when the active program execution of all physical cores except for the single physical core is suspended, to validate a signature of the microcode patch using a public key;
applying the microcode patch to the processor in response to validating the signature of the microcode patch using the public key; and
resuming the active program execution of all physical cores in the processor after the microcode patch has been applied without resetting the hypervisor or the virtual machine of the host computing device.

2. The computer implemented method of claim 1 , wherein the microcode patch for the processor is received from a second host computing device over a network connection.

3. The computer implemented method of claim 1 , wherein the public key used to validate the signature of the microcode patch is stored in at least one of: a trusted platform module (TPM) on the host computing device or a remote trusted host computing device.

4. The computer implemented method of claim 1 , wherein the public key used to validate the signature of the microcode patch is written to the processor on at least one of: programmable read-only memory (PROM), field programmable read-only memory (FPROM), one-time programmable non-volatile memory (OTP NVM) or erasable programmable read-only memory (EPROM).

5. The computer implemented method of claim 1 , wherein the microcode patch further includes at least one replacement microcode instruction and an instruction pointer identifying one or more native microcode instructions that are to be replaced by the at least one replacement microcode instruction on the processor.

6. The computer implemented method of claim 1 , further comprising:
storing the microcode patch in a level 2 cache on the host computing device;
sealing access to the level 2 cache on the host computing device;
authenticating the microcode patch in the level 2 cache; and
applying the microcode patch to the processor of the host computing device in response to authenticating the microcode patch in the level 2 cache.

7. The computer implemented method of claim 1 , wherein suspending the active program execution of all physical cores further includes:
entering a native processor debugging mode of the processor of the host computing device.

8. The computer implemented method of claim 1 , wherein the microcode patch further includes:
one or more replacement microcode instructions and an instruction pointer identifying one or more native microcode instructions that are to be replaced by the one or more replacement microcode instruction on the processor; and wherein the one or more replacement microcode instructions are stored in random access memory of the host computing device.

9. The computer implemented method of claim 1 , wherein receiving the microcode patch further comprises:
reading the microcode patch into memory of the host computing device from a remote computing device over a network connection.

10. The computer implemented method of claim 1 , wherein the processor further includes a hardware decoding unit, wherein during the execution in the processor, the hardware decoding unit translates each of a plurality of instructions read from memory into a sequence of microcode instructions to be executed in the processor.

11. A computing system, comprising:
at least one processor; and
memory including instructions that, when executed by the at least one processor, cause the computing system to:
receive, to a host computing device, a microcode patch for a processor of the host computing device, including a hypervisor hosting a virtual machine, the microcode patch signed using a private key;
detect a system management interrupt on the host computing device;
enter a system management mode (SMM) on the host computing device and suspending active program execution of all physical cores in the processor except for a single physical core in the processor;
attempt, by the single physical core executing SMM code when the active program execution of all physical cores except for the single physical core is suspended, to validate a signature of the microcode patch using a public key;
apply the microcode patch to the processor in response to validating the signature of the microcode patch using the public key; and
resume the active program execution of all physical cores in the processor after the microcode patch has been applied without resetting the hypervisor or the virtual machine of the host computing device.

12. The computing system of claim 11 , wherein the microcode patch further includes at least one replacement microcode instruction and an instruction pointer identifying one or more native microcode instructions that are to be replaced by the at least one replacement microcode instruction on the processor.

13. The computing system of claim 11 , wherein the instructions further cause the computing system to:
store the microcode patch in a level 2 cache on the host computing device;
seal access to the level 2 cache on the host computing device;
authenticate the microcode patch in the level 2 cache; and
apply the microcode patch to the processor of the host computing device in response to authenticating the microcode patch in the level 2 cache.

14. The computing system of claim 11 , wherein the processor utilizes a third key to verify the public key stored in a trusted platform module (TPM).

15. A non-transitory computer readable storage medium storing one or more sequences of instructions executed by one or more processors to:
receive, to a host computing device, a microcode patch for a processor of the host computing device, including a hypervisor hosting a virtual machine, the microcode patch signed using a private key;
detect a system management interrupt on the host computing device;
enter a system management mode (SMM) on the host computing device and suspending active program execution of all physical cores in the processor except for a single physical core in the processor;
attempt, the single physical core executing SMM code when the active program execution of all physical cores except for the single physical core is suspended, to validate a signature of the microcode patch using a public key;
apply the microcode patch to the processor in response to validating the signature of the microcode patch using the public key; and
resume the active program execution of all physical cores in the processor after the microcode patch has been applied without resetting the hypervisor or the virtual machine of the host computing device.

16. The non-transitory computer readable storage medium of claim 15 , further comprising instructions executed by the one or more processors to:
store the microcode patch in a level 2 cache on the host computing device;
seal access to the level 2 cache on the host computing device;
authenticate the microcode patch in the level 2 cache; and
apply the microcode patch to the processor of the host comp

Assignees

• Amazon Tech Inc

Inventors

• Potlapally Nachiketh Rao
• Marr Michael David

Classifications

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title

• H04L9/30

  Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy · CPC title

• G06F21/572 Primary

  Secure firmware programming, e.g. of basic input output system [BIOS] · CPC title

• H04L9/0838

  Key agreement, i.e. key establishment technique in which a shared key is derived by parties as a function of information contributed by, or associated with, each of these (network architectures or network communication protocols for key exchange in a packet data network H04L63/061) · CPC title