Three-dimensional semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2020258905-A1
Application number	US-202016856663-A
Country	US
Kind code	A1
Filing date	Apr 23, 2020
Priority date	Nov 9, 2017
Publication date	Aug 13, 2020
Grant date	—

Abstract

A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

First claim

What is claimed is:

1 . A three-dimensional semiconductor memory device, comprising:
an electrode structure comprising a plurality of gate electrodes and a plurality of insulating layers, wherein the gate electrodes and the insulating layers are alternately stacked on a substrate, and a side surface of the electrode structure is recessed in areas corresponding to the gate electrodes to define a plurality of recess regions; a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and crossing the side surface of the electrode structure; a plurality of first charge trap layers respectively disposed in the recess regions of the electrode structure, wherein the first charge trap layers surround the semiconductor pattern; a tunnel insulating layer disposed between the first charge trap layers and the semiconductor pattern; a blocking insulating layer disposed between the first charge trap layers and the electrode structure; and a second charge trap layer, wherein the second charge trap layer continuously extends between the blocking insulating layer and the first charge trap layers, and the second charge trap layer continuously extends between the tunnel insulating layer and the first charge trap layers, wherein the first charge trap layers are formed of a material having a first energy band gap, and the second charge trap layer is formed of a material having a second energy band gap larger than the first energy band gap, wherein a thickness of the second charge trap layer is smaller than a thickness of the tunnel insulating layer in a second direction, wherein the second direction is substantially parallel to the top surface of the substrate.

2 . A three-dimensional semiconductor memory device, comprising:
an electrode structure comprising a plurality of gate electrodes and a plurality of insulating layers, wherein the gate electrodes and the insulating layers are alternately stacked on a substrate; a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure; a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure; a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure; and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer, wherein the charge storing layer has a first thickness in first regions adjacent to the gate electrodes, and a second thickness in second regions adjacent to the insulating layers, wherein the second thickness is less than the first thickness, wherein the charge storing layer comprises a plurality of first charge trap layers respectively disposed in the first regions, and a second charge trap layer, wherein the first charge trap layers have a first energy band gap, and the second charge trap layer has a second energy band gap greater than the first energy band gap.

3 . The three-dimensional semiconductor memory device of claim 2 , wherein side surfaces of the insulating layers are spaced apart from a side surface of the semiconductor pattern by a first distance in a second direction substantially parallel to the top surface of the substrate, and side surfaces of the gate electrodes are spaced apart from the side surface of the semiconductor pattern by a second distance,
wherein the second distance is larger than the first distance in the second direction.

4 . The three-dimensional semiconductor memory device of claim 2 , wherein the second energy band gap is smaller than a third energy band gap of the tunnel insulating layer.

5 . The three-dimensional semiconductor memory device of claim 2 , wherein the first charge trap layers are embedded in the second charge trap layer.

6 . The three-dimensional semiconductor memory device of claim 2 , wherein the second charge trap layer extends in the first direction from the first regions to the second regions.

7 . The three-dimensional semiconductor memory device of claim 2 , wherein the first charge trap layers are disposed in the first regions of the charge storing layer, and are spaced apart from one another in the first direction.

8 . The three-dimensional semiconductor memory device of claim 2 , wherein the second charge trap layer covers top and bottom surfaces of each of the first charge trap layers.

9 . The three-dimensional semiconductor memory device of claim 2 , wherein the second charge trap layer continuously extends between the blocking insulating layer and the first charge trap layers, and the second charge trap layer continuously extends between the tunnel insulating layer and the first charge trap layers.

10 . The three-dimensional semiconductor memory device of claim 2 , wherein the second charge trap layer is disposed between the blocking insulating layer and the first charge trap layers.

11 . The three-dimensional semiconductor memory device of claim 2 , wherein the second charge trap layer is disposed between the tunnel insulating layer and the first charge trap layers.

12 . A charge storing layer of a three-dimensional semiconductor memory device, comprising:
a plurality of first charge trap layers having a first energy band gap; and a second charge trap layer having a second energy band gap larger than the first energy band gap, wherein the first charge trap layers are embedded in the second charge trap layer between gate electrodes of the three-dimensional semiconductor memory device and a semiconductor pattern of the three-dimensional semiconductor memory device.

13 . The charge storing layer of claim 12 , wherein the charge storing layer has a first thickness between the gate electrodes and the semiconductor pattern in a first direction substantially parallel to a top surface of a substrate on which the charge storing layer is formed, and has a second thickness between insulating layers of the three-dimensional semiconductor memory device and the semiconductor pattern in the first direction, wherein the second thickness is smaller than the first thickness.

14 . The charge storing layer of claim 12 , wherein the second charge trap layer contacts top and bottom surfaces of each of the first charge trap layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Kyunghwan
• Kim Yongseok
• Kim Byoung-Taek
• Kim Tae Hun
• Seo Dongkyun
• Lim Junhee

Classifications

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D30/699

  having the gate at least partly formed in a trench · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title