Silicon-on-insulator die support structures and related methods

Patent metadata

Field	Value
Publication number	US-2020258751-A1
Application number	US-202016861810-A
Country	US
Kind code	A1
Filing date	Apr 29, 2020
Priority date	Aug 17, 2017
Publication date	Aug 13, 2020
Grant date	—

Abstract

Implementations of a silicon-in-insulator (SOI) semiconductor die may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be included through a silicon layer coupled to a insulative layer.

First claim

What is claimed is:

1 . A silicon-in-insulator (SOI) semiconductor die comprising:
a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof; wherein the first largest planar surface, the second largest planar surface, and the thickness are comprised by a silicon layer coupled to a insulative layer.

2 . The die of claim 1 , wherein a warpage of one of the first largest planar surface or the second largest planar surface is less than 200 microns.

3 . The die of claim 1 , wherein the thickness is between 0.1 microns and 125 microns.

4 . The die of claim 1 , wherein a perimeter of the SOI semiconductor die is rectangular and a size of the SOI semiconductor die is at least 6 mm by 6 mm.

5 . The die of claim 1 , wherein a perimeter of the SOI semiconductor die is rectangular and a size of the SOI semiconductor die is 211 mm by 211 mm or smaller.

6 . The die of claim 1 , wherein the permanent die support structure comprises a mold compound.

7 . The die of claim 1 , wherein the one of the permanent die support structure, the temporary die support structure, or any combination thereof comprises a perimeter comprising a closed shape.

8 . The die of claim 1 , further comprising a second permanent die support structure, a second temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof.

9 . The die of claim 1 , wherein the permanent die support structure, the temporary die support structure, or any combination thereof comprises two or more layers.

10 . A method of making silicon-on-insulator (SOI) die, the method comprising:
forming a ring around a perimeter of a second side of a silicon substrate through backgrinding the second side of the substrate to a desired substrate thickness; depositing an insulative layer onto the second side of the silicon substrate after backgrinding; forming one of a permanent die support structure, a temporary die support structure, or any combination thereof on the second side of the substrate; removing the ring around the perimeter of the second side of the silicon substrate; and singulating the silicon substrate into a plurality of SOI die.

11 . The method of claim 10 , further comprising forming a plurality of semiconductor devices on the first side of the silicon substrate, the first side opposite the second side of the silicon substrate.

12 . The method of claim 10 , further comprising stress relief etching the second side of the silicon substrate.

13 . The method of claim 10 , wherein the insulative layer is deposited using one of co-evaporation and co-sputtering.

14 . The method of claim 13 , further comprising dissipating heat through a heat dissipation device during deposition of the insulative layer.

15 . The method of claim 10 , wherein the method does not comprise implanting hydrogen.

16 . A method of making silicon-on-insulator (SOI) die, the method comprising:
thinning a second side of a silicon substrate to a desired thickness; depositing an insulative layer over a conductive layer; forming one of a permanent die support structure, a temporary die support structure, or any combination thereof on the insulative layer; and singulating the silicon substrate into a plurality of SOI die.

17 . The method of claim 16 , further comprising depositing a conductive layer onto the second side of the silicon substrate.

18 . The method of claim 17 , further comprising patterning the conductive layer.

19 . The method of claim 17 , wherein the conductive layer comprises titanium.

20 . The method of claim 16 , wherein the insulative layer is deposited using one of co-evaporation and co-sputtering.

Assignees

• Semiconductor Components Ind

Inventors

• Seddon Michael J
• Carney Francis J
• Kurose Eiji
• Chew Chee Hiong
• Wang Soon Wei

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title