Splitting load hit store table for out-of-order processor

Patent metadata

Field	Value
Publication number	US-2020257535-A1
Application number	US-202016860400-A
Country	US
Kind code	A1
Filing date	Apr 28, 2020
Priority date	Nov 2, 2018
Publication date	Aug 13, 2020
Grant date	—

Abstract

According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.

First claim

What is claimed is:

1 . A computer-implemented method for executing one or more out-of-order instructions by a processing unit, the method comprising:
decoding an instruction to be executed; based on a determination that the instruction is a store instruction, and a determination that the instruction uses a pre-selected dedicated register, using as a load-hit-store (LHS) table for the store instruction a pre-selected dedicated LHS table;
adding one or more parameters of the store instruction in the LHS table by generating an ITAG for the store instruction; and
dispatching the store instruction for execution to an issue queue with the ITAG.

2 . The computer-implemented method of claim 1 , wherein, based on the determination that the instruction is a store instruction, and a determination that the instruction does not use the pre-selected dedicated register, using as the LHS table for the store instruction, a first split LHS table from a plurality of LHS tables, wherein the first split LHS table is identified by performing a mod operation using one or more operands from the store instruction.

3 . The computer-implemented method of claim 2 , wherein the operands of the store instruction used for determining the first split LHS table include a base register (RB).

4 . The computer-implemented method of claim 2 , wherein the operands of the store instruction used for determining the first split LHS table include a displacement.

5 . The computer-implemented method of claim 2 , wherein the mod operation is performed on a result of a function of an index register, a base register, and a displacement of the store instruction.

6 . The computer-implemented method of claim 1 , further comprising:
prior to adding the one or more operands of the store instruction in an entry in the LHS table, checking for an existing entry corresponding to the store instruction in the LHS table; and based on identifying the existing entry, invalidating the existing entry prior to adding the entry.

7 . The computer-implemented method of claim 1 , further comprising:
based on a determination that the instruction is a load instruction, and the load instruction uses the pre-selected dedicated register, using the pre-selected dedicated LHS table as the LHS table for the load instruction.

8 . A processing unit for executing one or more instructions, the processing unit comprising:
a load hit store (LHS) table comprising a plurality of split LHS tables; and the processing unit configured to execute instructions by performing a method that comprises:
decoding an instruction to be executed;
based on a determination that the instruction is a store instruction, and a determination that the instruction uses a pre-selected dedicated register, using a pre-selected dedicated split LHS table from the plurality of split LHS tables as an LHS table for the store instruction;
adding one or more parameters of the store instruction in the LHS table by generating an ITAG for the store instruction; and
dispatching the store instruction for execution to an issue queue with the ITAG.

9 . The processing unit of claim 8 , wherein, based on the determination that the instruction is a store instruction, and a determination that the instruction does not use the pre-selected dedicated register, using as the LHS table for the store instruction, a first split LHS table from the plurality of LHS tables, wherein the first split LHS table is identified by performing a mod operation using one or more operands from the store instruction.

10 . The processing unit of claim 8 , wherein the operands of the store instruction used for determining the first split LHS table include an index register (RA), and a base register (RB).

11 . The processing unit of claim 8 , wherein the operands of the store instruction used for determining the first split LHS table include a displacement.

12 . The processing unit of claim 8 , wherein the mod operation is performed on a result of a function of an index register, a base register, and a displacement of the store instruction.

13 . The processing unit of claim 8 , further comprising:
prior to adding the one or more operands of the store instruction in an entry in the first split LHS table, checking for an existing entry corresponding to the store instruction in the first split LHS table; and based on identifying the existing entry, invalidating the existing entry prior to adding the entry.

14 . The processing unit of claim 8 , further comprising:
based on a determination that the instruction is a load instruction, and that the load instruction uses the pre-selected dedicated register, using the pre-selected dedicated LHS table as the LHS table for the load instruction.

15 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processing unit to cause the processing unit to perform operations comprising:
decoding an instruction to be executed; based on a determination that the instruction is a store instruction, and a determination that the instruction uses a pre-selected dedicated register, using, as a split load-hit-store (LHS) table for the store instruction, a pre-selected dedicated split LHS table from a plurality of LHS tables from the processing unit;
adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction; and
dispatching the store instruction for execution to an issue queue with the ITAG.

16 . The computer program product of claim 15 , wherein, based on the determination that the instruction is a store instruction, and a determination that the instruction does not use the pre-selected dedicated register, using as the LHS table for the store instruction, a first split LHS table from a plurality of LHS tables, wherein the first split LHS table is identified by performing a mod operation using one or more operands from the store instruction.

17 . The computer program product of claim 16 , wherein the mod operation is performed on a result of a function of an index register, a base register, and a displacement of the store instruction.

18 . The computer program product of claim 15 , further comprising:
prior to adding the one or more operands of the store instruction in an entry in the first split LHS table, checking for an existing entry corresponding to the store instruction in the first split LHS table; and based on identifying the existing entry, invalidating the existing entry prior to adding the entry.

19 . The computer program product of claim 15 , further comprising:
based on a determination that the instruction is a load instruction, and the load instruction uses the pre-selected dedicated register, using the pre-selected dedicated LHS table as the LHS table for the load instruction.

20 . The computer program product of claim 19 , further comprising:
based on identifying the existing entry for the load instruction, dispatching the load instruction with the ITAG from the existing entry.

Assignees

• IBM

Inventors

• Fatehi Ehsan
• Eickemeyer Richard J
• Gieske Edmund J

Classifications

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3824

  Operand accessing · CPC title