Thread priorities using misprediction rate and speculative depth
US-11847458-B2 · Dec 19, 2023 · US
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Fatehi Ehsan patents
Fatehi Ehsan is listed as an inventor on 20 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Fatehi Ehsan |
| Total patents | 20 |
| First publication | May 24, 2018 |
| Latest publication | Dec 19, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Thread priorities using misprediction rate and speculative depth
US-2023004394-A1 · Jan 5, 2023 · US
Flushing of instructions based upon a finish ratio and/or moving a flush point in a processor
US-11520591-B2 · Dec 6, 2022 · US
Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-through
US-11416257-B2 · Aug 16, 2022 · US
Intelligent balanced flushing in a processor
US-2021303311-A1 · Sep 30, 2021 · US
Preventing operand store compare conflicts using conflict address data tables
US-11080060-B2 · Aug 3, 2021 · US
Splitting load hit store table for out-of-order processor
US-10942743-B2 · Mar 9, 2021 · US
Tagged indirect branch predictor (TIP)
US-10936318-B2 · Mar 2, 2021 · US
Resolving operand store compare conflicts
US-10824430-B1 · Nov 3, 2020 · US
Resolving operand store compare conflicts
US-2020341771-A1 · Oct 29, 2020 · US
Recent patents
Latest publications not already listed above.
Resolving operand store compare conflicts
US-2020341769-A1 · Oct 29, 2020 · US
Tagged branch orientation predictor
US-2020326951-A1 · Oct 15, 2020 · US
Splitting load hit store table for out-of-order processor
US-2020257535-A1 · Aug 13, 2020 · US
Splitting load hit store table for out-of-order processor
US-10725783-B2 · Jul 28, 2020 · US
Tagged indirect branch predictor (tip)
US-2020150968-A1 · May 14, 2020 · US
Splitting load hit store table for out-of-order processor
US-2020142702-A1 · May 7, 2020 · US
Providing Real-Time Predictive Feedback During Logic Design
US-2020074276-A1 · Mar 5, 2020 · US
Dynamic adjustment of issue-to-issue delay between dependent instructions
US-2019377577-A1 · Dec 12, 2019 · US
Network-aware cache coherence protocol enhancement
US-10402327-B2 · Sep 3, 2019 · US
Network-aware cache coherence protocol enhancement
US-2018143905-A1 · May 24, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| IBM | 18 |
| Advanced Micro Devices Inc | 2 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F9/3838 | 8 |
| G06F9/3834 | 8 |
| G06F9/30043 | 8 |
| G06F9/3851 | 4 |
| G06F9/3867 | 4 |