Package-embedded thin-film capacitors, package-integral magnetic inductors, and methods of assembling same

Patent metadata

Field	Value
Publication number	US-2020251467-A1
Application number	US-202016855376-A
Country	US
Kind code	A1
Filing date	Apr 22, 2020
Priority date	Jun 25, 2018
Publication date	Aug 6, 2020
Grant date	—

Abstract

Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

First claim

1 . A semiconductor package substrate, comprising:
a first build-up film including a first surface; a second and adjacent build-up film including a recess that abuts the first surface; and a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess.

2 . The semiconductor package substrate of claim 1 , further including a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film.

3 . The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:
a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor.

4 . The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side further including:
a ball-pad array on the die side, where ball-pad pad array is exposed through a die-side solder resist semiconductive device contacting the die side, wherein the ball-pad array is coupled to the integral magnetic inductor, wherein the ball-pad array forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor.

5 . The semiconductor package substrate of claim I, further including:
a thin-film capacitor, wherein the thin-film capacitor is seated on the first surface, and at least partially embedded in the second and adjacent build-up film, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side; and a first capacitor via that communicates to the die side and that contacts the thin-film capacitor.

6 . The semiconductor package substrate of claim 5 , further including a subsequent capacitor via that communicates to the die side and that contacts the thin-film capacitor.

7 . The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, and the magnetic inductor is a first magnetic inductor, further including:
a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent the first magnetic inductor, wherein the subsequent magnetic inductor includes a subsequent inductor trace and a subsequent first magnetic-particle body within the recess, and a subsequent complementary magnetic-particle body that contacts the subsequent inductor trace, the subsequent first magnetic-particle body and the first build-up film.

8 . The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the recess is a first recess, and wherein the magnetic inductor is a first magnetic inductor, further including:
a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent the first magnetic inductor, wherein the subsequent magnetic inductor includes two subsequent inductor traces and a subsequent first magnetic-particle body within a subsequent recess with the second and adjacent build-up film, and a subsequent complementary magnetic-particle body that contacts the two subsequent inductor traces, the subsequent first magnetic-particle body and the first build-up film.

9 . The semiconductor package substrate of claim 2 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:
a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the integral magnetic inductor; an electrical bump on the land side; and a board contacting the electrical bump.

10 . The semiconductor package substrate of claim 1 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, further including:
a package via that communicates from the die side, through the first build-up film, the second and adjacent build-up film, and that further communicates to the land side.

11 . The semiconductor package substrate of claim 5 , wherein the thin-film capacitor includes, beginning at the first surface, a copper-containing layer, a nickel-containing layer, a barium titanate (BTO) containing layer and a copper-containing layer.

12 . The semiconductor package substrate of claim 5 , wherein the thin-film capacitor includes, beginning at the first surface, a first metal-containing layer, a subsequent metal-containing layer different from the first metal-containing layer, a dielectric layer and a third metal-containing layer.

13 . A semiconductor package substrate, comprising:
a first build-up film including a first surface; a second and adjacent build-up film including a recess that abuts the first surface, wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side; a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess; a complementary magnetic-particle body that contacts the inductor trace, the first magnetic-particle body and the first build-up film; and a semiconductive device contacting the die side, wherein the semiconductive device is coupled to the integral magnetic inductor, wherein the semiconductive device forms a die shadow on the die side, and wherein the die shadow overlaps the integral magnetic inductor.

14 . The semiconductor package substrate of claim 13 , wherein the first build-up film and the second and adjacent build-up film are part of a semiconductor package substrate portion that includes a die side and a land side, wherein the recess is a first recess, and wherein the magnetic inductor is a first magnetic inductor, further including:
a subsequent magnetic inductor, wherein the subsequent magnetic inductor is adjacent the first magnetic inductor, wherein the subsequent magnetic inductor includes two subsequent inductor traces and a subsequent first magnetic-particle body within a subsequent recess with the second and adjacent build-up film, and a subsequent complementary magnetic-particle body that contacts the two subsequent inductor traces, the subsequent first magnetic-particle body and the first build-up film.

15 . A computing system, comprising:
a first build-up film of a semiconductor package substrate, wherein the first build-up film includes a first surface, and wherein the semiconductor package substrate includes a die side and a land side; a second and adjacent build-up film including a recess that abuts the first surface; an integral magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess; a semiconductive device contacting the die side, wherein the semiconductive device is coupled to integral magnetic inductor, wherein the sem

Assignees

• Intel Corp

Inventors

• Xu Cheng
• Jain Rahul
• Kim Seo Young
• Lee Kyu Oh
• Park Ji Yong
• Vadlamani Sai
• Zhao Junnan

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title