Device and method for alignment of vertically stacked wafers and die

Patent metadata

Field	Value
Publication number	US-2020203286-A1
Application number	US-202016808090-A
Country	US
Kind code	A1
Filing date	Mar 3, 2020
Priority date	Dec 30, 2009
Publication date	Jun 25, 2020
Grant date	—

Abstract

A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

First claim

1 . A device, comprising:
a first wafer having a first surface opposite a second surface; a first alignment structure having:
a first discrete base adjacent to the first surface of the first wafer;
a first plurality of discrete transmission columns each extending directly from the first discrete base through the first wafer to the second surface and each exposed from the second surface, the first plurality of discrete transmission columns including a first discrete transmission column and a second discrete transmission column, the first discrete transmission column and the second discrete transmission column being electrically connected to one another through the first discrete base; and
a second alignment structure spaced apart from the first alignment structure, the second alignment structure having:
a second discrete base adjacent to the first surface of the first wafer, the second discrete base being spaced apart from the first discrete base; and
a second plurality of transmission columns extending from the second discrete base through the first wafer to the second surface, the second plurality of discrete transmission columns including a third discrete transmission column and a fourth discrete transmission column, the third discrete transmission column and the fourth discrete transmission column being electrically connected to one another through the second discrete base.

2 . The device of claim 1 wherein a surface of ends of the transmission columns is coplanar with the second surface.

3 . The device of claim 1 wherein the transmission columns are electrically conductive.

4 . The device of claim 1 , further comprising:
a second wafer on the first wafer, the second wafer having a first surface opposite a second surface; a third alignment structure having a third discrete base adjacent to the first surface of the second wafer, the third alignment structure including a third plurality of transmission columns extending from the third discrete base of the third alignment structure through the second wafer to the second surface of the second wafer.

5 . The device of claim 4 wherein the third alignment structure and the first alignment structure are aligned.

6 . The device of claim 4 wherein the transmission columns of the first alignment structure are aligned with respective ones of the alignment columns of the third alignment structure.

7 . A semiconductor wafer, comprising:
a first surface and a second surface opposite to the first surface; a first conductive pad adjacent to the first surface; and a plurality of conductive columns each including a first end and a second end, the first end directly contacting the first conductive pad, and the second end being a part of the second surface.

8 . The semiconductor wafer of claim 7 , wherein the first conductive pad is of a non-rectangular shape.

9 . The semiconductor wafer of claim 7 , wherein the first conductive pad is in a kerf region of the first surface.

10 . The semiconductor wafer of claim 7 , wherein the first conductive pad and the plurality of conductive columns are of a same material.

11 . The semiconductor wafer of claim 7 , wherein a surface of the first conductive pad protrudes beyond the first surface.

12 . The semiconductor wafer of claim 7 , wherein an end surface of the second end of a conductive column of the plurality of conductive columns is exposed from the second surface.

13 . The semiconductor wafer of claim 7 , wherein the plurality of conductive columns includes a first conductive column, a second conductive column and a third conductive column, the first conductive column and the second conductive column arranged in a first direction, and the first conductive column and the third conductive column arranged in a second direction that crosses the first direction.

14 . The semiconductor wafer of claim 7 , wherein the plurality of conductive columns are arranged in a two dimensional pattern.

15 . A device, comprising:
a first wafer that have a first surface and a second surface opposite to the first surface, the first wafer having a first capacitive element buried and adjacent to the second surface; and a second wafer that have a third surface and a fourth surface opposite to the third surface, the second wafer coupled to the first wafer by the second surface of the first wafer and the third surface of the second wafer, the second wafer having a second capacitive element buried and adjacent to the third surface.

16 . The device of claim 15 wherein a capacitance value between the first capacitive element and the second capacitive element is variable based on a relative position between the first wafer and the second wafer.

17 . The device of claim 15 , wherein the first capacitive element is in a kerf region of the first wafer.

18 . The device of claim 15 , further comprising an alignment circuit communicatively associated to at least one of the first capacitive element or the second capacitive element, the alignment circuit configured to obtain a capacitance value between the first capacitive element and the second capacitive element.

19 . The device of claim 18 , wherein the alignment circuit is included in a kerf region of the first wafer.

20 . The device of claim 15 , wherein the first wafer includes an embedded storage unit storing a parameter of the first capacitive element.

Assignees

• St Microelectronics Inc

Inventors

• Zhang John H
• Kleemeier Walter
• Ferreira Paul
• Sampson Ronald K

Classifications

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/232

  comprising connection or disconnection of parts of a device in response to a measurement · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title