Selective deposition with atomic layer etch reset

US2020118809A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020118809-A1
Application numberUS-201916713557-A
CountryUS
Kind codeA1
Filing dateDec 13, 2019
Priority dateApr 19, 2017
Publication dateApr 16, 2020
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Methods are provided for conducting a deposition on a semiconductor substrate by selectively depositing a material on the substrate. The substrate has a plurality of substrate materials, each with a different nucleation delay corresponding to the material deposited thereon. Specifically, the nucleation delay associated with a first substrate material on which deposition is intended is less than the nucleation delay associated with a second substrate material on which deposition is not intended according to a nucleation delay differential, which degrades as deposition proceeds. A portion of the deposited material is etched to reestablish the nucleation delay differential between the first and the second substrate materials. The material is further selectively deposited on the substrate.

First claim

Opening claim text (preview).

What is claimed is: 1 . An apparatus for processing substrates, the apparatus comprising: one or more process chambers, each process chamber having a chuck; one or more gas inlets into the process chambers and associated flow-control hardware; and a controller having a processor and a memory, wherein the processor and the memory are communicatively connected with one another, the at least one processor is at least operatively connected with the flow-control hardware, and the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware by: selectively depositing a material on a semiconductor substrate, the substrate comprising a plurality of substrate materials having different nucleation delays corresponding to the material deposited thereon according to a nucleation delay differential; etching a portion of the material deposited on the substrate to reestablish the nucleation delay differential between the substrate materials; and further selectively depositing the material on the substrate. 2 . The apparatus of claim 1 , wherein the selectively depositing a material on a semiconductor substrate and etching a portion of the material deposited on the substrate are performed without breaking vacuum. 3 . The apparatus of claim 1 , wherein the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow-control hardware by: (a) exposing a substrate housed in a chamber to alternating pulses of a first reactant and a second reactant to deposit a film over the substrate, the substrate having a first substrate material on which deposition of the film is intended and a second substrate material on which deposition of the film is not intended, the second substrate material being different from the first substrate material, and the nucleation delay for the first substrate material being less than the nucleation delay for the second substrate material according to a nucleation delay differential, which degrades upon proceeding with the deposition; (b) exposing a substrate housed in a chamber to alternating pulses of an etching gas and a removal gas to etch a portion of the deposited material to reset the nucleation delay differential between the first and second substrate materials 4 . The apparatus of claim 3 , further comprising repeating (a) and (b) in the same chamber. 5 . The apparatus of claim 3 , wherein the (a) and (b) are performed without breaking vacuum. 6 . An apparatus for processing substrates, the apparatus comprising: a process chamber having a substrate-supporting chuck; one or more gas inlets into the process chamber and associated flow-control hardware; and a controller having a processor and a memory, wherein the processor and the memory are communicatively connected with one another, the processor is at least operatively connected with the flow-control hardware, and the memory stores computer-executable instructions for controlling the processor to at least control the flow-control hardware by: (a) exposing a substrate housed in the process chamber to alternating pulses of a first reactant and a second reactant to deposit a film over the substrate, the substrate having a first substrate material on which deposition of the film is intended and a second substrate material on which deposition of the film is not intended, the second substrate material being different from the first substrate material, and a nucleation delay for the first substrate material being less than a nucleation delay for the second substrate material according to a nucleation delay differential, which degrades upon proceeding with the film deposition; and (b) exposing the substrate housed in the chamber to alternating pulses of an etching gas and a removal gas to etch a portion of the film deposited in (a) to reset the nucleation delay differential between the first and second substrate materials; wherein (a) and (b) result in net deposition of the film on the first substrate material. 7 . The apparatus of claim 6 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware by repeating (a) and (b) in the same chamber. 8 . The apparatus of claim 6 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that (a) and (b) are performed without breaking vacuum. 9 . The apparatus of claim 7 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that (a) and (b) are performed without breaking vacuum. 10 . The apparatus of claim 6 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that the first reactant is a deposition precursor to modify a surface of the substrate, and the second reactant is a reducing agent to deposit the material. 11 . The apparatus of claim 6 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that the material to be deposited is aluminum nitride (AlN). 12 . The apparatus of claim 11 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that trimethlyaluminum provides aluminum for the aluminum nitride to be deposited. 13 . The apparatus of claim 12 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that the trimethlyaluminum is deposited in a temperature range from 250° C. to 350° C. 14 . The apparatus of claim 6 , wherein the memory further stores computer-executable instructions for controlling the processor to at least control the flow-control hardware so that the removal gas is a carrier gas selected from the group consisting of N 2 , Ar, He, and Ne.

Assignees

Inventors

Classifications

  • characterised by the construction of the load-lock chamber · CPC title

  • surrounding a central transfer chamber · CPC title

  • of materials not containing Si, e.g. PZT or Al2O3 · CPC title

  • the material containing aluminium, e.g. Al2O3 · CPC title

  • deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

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What does patent US2020118809A1 cover?
Methods are provided for conducting a deposition on a semiconductor substrate by selectively depositing a material on the substrate. The substrate has a plurality of substrate materials, each with a different nucleation delay corresponding to the material deposited thereon. Specifically, the nucleation delay associated with a first substrate material on which deposition is intended is less than…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P14/6339. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 16 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).