Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020105640-A1
Application number	US-201916373643-A
Country	US
Kind code	A1
Filing date	Apr 3, 2019
Priority date	Sep 27, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

A semiconductor device including a circuit substrate, a chip package, and a stiffener ring is provided. The chip package is disposed on and electrically connected to the circuit substrate, the chip package includes a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides. The stiffener ring is disposed on the circuit substrate, the stiffener ring includes first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides. The first stiffener portions are connected to the second stiffener portions, and the second stiffener portions is mechanically weaker than the first stiffener portions. A semiconductor device including stiffener lids is also provided.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a circuit substrate; a chip package disposed on and electrically connected to the circuit substrate, the chip package comprising a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides; and a stiffener ring disposed on the circuit substrate, the stiffener ring comprising first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides, the first stiffener portions are connected to the second stiffener portions, and the second stiffener portions being mechanically weaker than the first stiffener portions.

2 . The semiconductor device as claimed in claim 1 , wherein the chip package is surrounded by the stiffener ring.

3 . The semiconductor device as claimed in claim 1 , wherein the first stiffener portions and the second stiffener portions are substantially identical in thickness and the second stiffener portions are narrower than the first stiffener portions.

4 . The semiconductor device as claimed in claim 1 , wherein the first stiffener portions and the second stiffener portions are substantially identical in width and the second stiffener portions are thinner than the first stiffener portions.

5 . The semiconductor device as claimed in claim 4 , wherein the first stiffener portions are adhered with the circuit substrate through an adhesive.

6 . The semiconductor device as claimed in claim 5 , wherein gaps are between the circuit substrate and the second stiffener portions.

7 . The semiconductor device as claimed in claim 4 , wherein the first and second stiffener portions are adhered with the circuit substrate through an adhesive.

8 . The semiconductor device as claimed in claim 1 , wherein the second stiffener portions are thinner and/or narrower than the first stiffener portions.

9 . The semiconductor device as claimed in claim 1 , wherein the first stiffener portions and the second stiffener portions are different in dimension.

10 . The semiconductor device as claimed in claim 1 , wherein a first coefficient of thermal expansion (CTE) of the circuit substrate is greater than a second CTE of the chip package.

11 . The semiconductor device as claimed in claim 10 , wherein a third CTE of the stiffener ring is greater than the first CTE of the circuit substrate.

12 . The semiconductor device as claimed in claim 1 , wherein the stiffener ring further comprises a plurality of stiffener ribs extending along a direction substantially parallel with the pair of first parallel sides and connected to the second stiffener portions.

13 . The semiconductor device as claimed in claim 12 , wherein at least one gap is between at least one of the stiffener ribs and the circuit substrate.

14 . A semiconductor device, comprising:
a circuit substrate; a chip package disposed on and electrically connected to the circuit substrate, the chip package comprising a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides; and a pair of stiffener lids disposed on the circuit substrate, each stiffener lid among the pair of stiffener lids comprising a foot portion attached to the circuit substrate and a cover covering the foot portion, the pair of stiffener lids extending along a direction substantially parallel with the pair of first parallel sides and being spaced apart from each other, wherein the foot portion defines a space between the circuit substrate and the cover.

15 . The semiconductor device as claimed in claim 14 , wherein the chip package is exposed by a gap between the pair of stiffener lids.

16 . The semiconductor device as claimed in claim 14 further comprising a plurality of electronic components disposed on and electrically connected to the circuit substrate, wherein the electronic components are located in the space between the circuit substrate and the cover.

17 . A semiconductor device, comprising:
a circuit substrate; a chip package disposed on and electrically connected to the circuit substrate, the chip package comprising a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides; and a stiffener ring disposed on the circuit substrate, the stiffener ring comprising a ring body and a plurality of stiffener ribs surrounded by the ring body, wherein the stiffener ribs extend along a direction substantially parallel with the pair of first parallel sides.

18 . The semiconductor device as claimed in claim 17 , wherein the ring body comprises first stiffener portions extending along a direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along the direction substantially parallel with the pair of second parallel sides.

19 . The semiconductor device as claimed in claim 17 , wherein a first coefficient of thermal expansion (CTE) of the circuit substrate is greater than a second CTE of the chip package.

20 . The semiconductor device as claimed in claim 19 , wherein a third CTE of the stiffener ring is greater than the first CTE of the circuit substrate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chiu Chien-Chia
• Hsu Li-Han

Classifications

• H01L23/3121

  Electricity · mapped topic

• H01L23/04

  Electricity · mapped topic

• H01L23/16

  Electricity · mapped topic

• H01L23/10

  Electricity · mapped topic

• H01L23/40 Primary

  Electricity · mapped topic