Conductive Interconnect Structures in Integrated Circuits

Patent metadata

Field	Value
Publication number	US-2020105593-A1
Application number	US-201816178470-A
Country	US
Kind code	A1
Filing date	Nov 1, 2018
Priority date	Sep 27, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

First claim

1 . A method of forming a semiconductor device, the method comprising:
forming a dielectric layer over a substrate; forming an opening in the dielectric layer on the substrate; depositing a conductive seed layer along sidewalls and a bottom of the opening, wherein an oxide layer is formed on the conductive seed layer; removing at least a portion of the oxide layer from a surface of the conductive seed layer by soaking the substrate in a chemical bath; and after removing the oxide layer, electroplating a conductive layer on the conductive seed layer while the substrate is in the chemical bath.

2 . The method of claim 1 , further comprising:
prior to soaking the substrate in the chemical bath, exposing the oxide layer to hydrogen radicals.

3 . The method of claim 2 , wherein exposing the oxide layer to hydrogen radicals is performed at least in part using a remote plasma process.

4 . The method of claim 3 , wherein the remote plasma process is performed at a pressure between 10 mTorr and 500 mTorr, a temperature of 30° C. to 500° C., and a time period of 10 seconds to 50 seconds.

5 . The method of claim 2 , further comprising maintaining vacuum during and between the exposing the oxide layer to hydrogen radicals and the soaking the substrate.

6 . The method of claim 1 , wherein the chemical bath comprises CoSO 4 ·7H 2 O, citric acid, hydrochloric acid, and a Co suppressor.

7 . The method of claim 1 , wherein soaking the substrate in the chemical bath is performed for a time period from about 0.75 seconds to about 100 seconds prior to applying an electroplating current.

8 . The method of claim 1 , wherein soaking the substrate in the chemical bath is performed at a pressure between 1 mTorr and 1000 mTorr, and further comprising maintaining vacuum during and between the soaking the substrate in the chemical bath and electroplating a conductive layer on the conductive seed layer while the substrate is in the chemical bath.

9 . A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate; forming an opening in the first dielectric layer on the substrate; depositing a conductive seed layer along sidewalls and a bottom of the opening, wherein an oxide layer is formed over a surface of the conductive seed layer; placing the substrate in a vacuum chamber; performing a first pre-treatment process, the first pre-treatment process removing at least a first portion of the oxide layer; after performing the first pre-treatment process, performing a second pre-treatment process, the second pre-treatment process removing at least a second portion of the oxide layer, the second pre-treatment process comprising a soak in a chemical bath, the first pre-treatment process being different than the second pre-treatment process; and electroplating a conductive layer over the conductive seed layer prior to removing the substrate from the chemical bath.

10 . The method of claim 9 , wherein the conductive seed layer comprises cobalt.

11 . The method of claim 10 , wherein the first pre-treatment process comprises exposing the oxide layer to hydrogen radicals using a remote plasma process.

12 . The method of claim ii, wherein the substrate remains in the chemical bath between the second pre-treatment process and the electroplating.

13 . The method of claim 9 , further comprising, prior to depositing the conductive seed layer, forming a silicide region on the substrate in the opening.

14 . The method of claim 9 , wherein the substrate comprises a second dielectric layer and a metal feature in the second dielectric layer, the metal feature contacting the conductive layer.

15 . A method of forming a semiconductor device, the method comprising:
forming a first dielectric layer over a substrate, the substrate comprising a transistor, the transistor comprising a first source/drain region, a second source/drain region, a channel region, and a gate structure; forming an opening through the first dielectric layer to the first source/drain region; forming a cobalt seed layer along a bottom and sidewalls of the opening, wherein a cobalt oxide is formed on the cobalt seed layer; removing the cobalt oxide from the cobalt seed layer by exposing the cobalt seed layer to hydrogen radicals; placing the substrate into an electroplating bath for a delay period, an electroplating current being disabled during the delay period, cobalt oxide over the cobalt seed layer being removed during the delay period; and after waiting for the delay period, applying an electroplating current while the substrate remains in the electroplating bath.

16 . The method of claim 15 , further comprising generating the hydrogen radicals using a remote plasma process.

17 . The method of claim 15 , wherein an open circuit potential during the delay period is less than 0.1 volts.

18 . The method of claim 15 , wherein the delay period is less than 100 seconds.

19 . The method of claim 15 , wherein applying the electroplating current electroplates cobalt over the cobalt seed layer.

20 . The method of claim 19 , wherein cobalt completely fills the opening after the applying the electroplating current.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Jung-Tang
• Lien Shao Tzu
• Liao Chi-Hung
• Wu Szu-Hua
• Ou Yang Liang-Yueh
• Lee Chin-Szu

Classifications

• H10W20/4437

  the principal metal being a transition metal · CPC title

• H01J37/32357 Primary

  Generation remote from the workpiece, e.g. down-stream · CPC title

• H01L29/66545

  Electricity · mapped topic

• H01L21/76843

  Electricity · mapped topic

• H01L23/53209

  Electricity · mapped topic