Semiconductor Structure with Staggered Selective Growth

Patent metadata

Field	Value
Publication number	US-2020105591-A1
Application number	US-201916366984-A
Country	US
Kind code	A1
Filing date	Mar 27, 2019
Priority date	Sep 27, 2018
Publication date	Apr 2, 2020
Grant date	—

Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature. The staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated. The first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

First claim

What is claimed is:

1 . A semiconductor structure, comprising:
a semiconductor substrate; a first conductive feature and a second conductive feature disposed on the semiconductor substrate; and a staggered dielectric feature interposed between the first and second conductive feature, wherein the staggered dielectric feature includes first dielectric layers and second dielectric layers being interdigitated, wherein the first dielectric layers include a first dielectric material and the second dielectric layers include a second dielectric material being different from the first dielectric material.

2 . The semiconductor structure of claim 1 , further comprising:
a third conductive feature underlying and contacting the first conductive feature; a fourth conductive feature underlying and contacting the second conductive feature; and a dielectric spacer underlying and contacting the staggered dielectric feature.

3 . The semiconductor structure of claim 2 , wherein
the third conductive feature is a gate electrode; the fourth conductive feature is a contact to a source/drain feature; the first conductive feature is a first interconnect feature electrically connecting to the gate electrode; and the second conductive feature is a second interconnect feature electrically connecting to the contact.

4 . The semiconductor structure of claim 2 , wherein the staggered dielectric feature is aligned with and is completely overlapped with the dielectric spacer.

5 . The semiconductor structure of claim 1 , wherein the first dielectric material is a silicon-containing dielectric material and the second dielectric material is a metal-containing dielectric material.

6 . The semiconductor structure of claim 5 , wherein the first dielectric material includes one of silicon oxide, silicon nitride and silicon oxynitride, and the second dielectric material includes one of hafnium oxide, zirconium oxide, lanthanum oxide, and aluminum oxide.

7 . The semiconductor structure of claim 1 , wherein the first dielectric layers include a first number N 1 of the first dielectric layers; the second dielectric layers include a second number N 2 of the second dielectric layers; and at least one of N 1 and N 2 is equal or greater than 2.

8 . A method, comprising:
providing a semiconductor structure having a first conductive feature in a first region and a second conductive feature in a second region, and a dielectric spacer interposed between the first and second conductive features; selectively depositing a first dielectric film of a first dielectric material on the first contact, wherein the selectively depositing of the first dielectric film includes laterally extends the first dielectric film to the dielectric spacer; and selectively depositing a second dielectric film of a second dielectric material on the second contact, wherein the selectively depositing of the second dielectric film includes laterally extends the second dielectric film to a lateral extended portion of the first dielectric film over the dielectric spacer, wherein the second dielectric material is different from the first dielectric material in composition.

9 . The method of claim 8 , wherein
the dielectric spacer includes a first edge laterally contacting the first conductive feature and a second edge laterally contacting the second conductive feature; the selectively depositing of the first dielectric film includes laterally extends the first dielectric film to the second edge; and the selectively depositing of the second dielectric film includes laterally extends the second dielectric film over the firs dielectric film to the first edge.

10 . The method of claim 9 , further comprising:
selectively depositing a third dielectric film of the first dielectric material on the first dielectric film, wherein the selectively depositing of the third dielectric film includes laterally extends the third dielectric film over a laterally extended portion of the second dielectric film to the second edge; and selectively depositing a fourth dielectric film of the second dielectric material on the second dielectric film, wherein the selectively depositing of the fourth dielectric film includes laterally extends the fourth dielectric film to a lateral extended portion of the third dielectric film to the first edge.

11 . The method of claim 10 , wherein
the selectively depositing of the first dielectric film includes performing a first atomic layer deposition (ALD) process using a first precursor; and the selectively depositing of the second dielectric film includes performing a second ALD process using a second precursor being different from the first precursor.

12 . The method of claim 9 , further comprising repeatedly depositing the first dielectric material and the second dielectric material to form a collective dielectric layer of the first and second dielectric materials until a thickness of the collective dielectric layer reaches a desired thickness.

13 . The method of claim 12 , further comprising:
performing a first etching process to selectively etch the first dielectric material, thereby forming a first trench; and forming a first via in the first trench, wherein the first via electrically connects to the first conductive feature.

14 . The method of claim 13 , wherein
the performing of the first etching process to selectively etch the first dielectric material further includes forming a patterned mask with an opening to expose the first dielectric material by a lithography process; and the forming of the first via in the first trench includes depositing a conductive material in the first trench and performing a chemical mechanical polishing (CMP) process.

15 . The method of claim 14 , further comprising
performing a second etching process to selectively etch the second dielectric material, thereby forming a second trench; and forming a second via in the second trench, wherein the second via electrically connects to the second conductive feature.

16 . The method of claim 15 , wherein
the first via and the second via are isolated from each other by a staggered portion of the collective dielectric layer; the staggered portion includes the first dielectric material and the second dielectric material interdigitated; the first conductive feature is a gate electrode; and the second conductive feature is a contact landing on a source/drain feature.

17 . The method of claim 8 , further comprising forming an inhibitor on the second conductive feature in the second region before the selectively depositing of the first dielectric film of the first dielectric material on the first conductive feature.

18 . A method, comprising:
providing a semiconductor structure that includes a first conductive feature in a first region, a second conductive feature in a second region, and a dielectric spacer in a third region interposing between the first and second regions; selectively depositing a first dielectric material in the first region, wherein the selectively depositing of the first dielectric material includes laterally extending the first dielectric material to the third region; selectively depositing a second dielectric material in the second region, wherein the selectively depositing of the second dielectric material includes laterally extending the second dielectric material to the third region, wherein the second dielectric material is different from the first dielectric material in composition; and repeatedly depositing the first and second dielectric mat

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin zhi-chang
• Tsai Teng-Chun
• Wu wei-hao

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H01L23/53295

  Electricity · mapped topic

• H01L21/0228

  Electricity · mapped topic

• H01L21/76837

  Electricity · mapped topic

• H01L29/4232

  Electricity · mapped topic