Self-aligned spacers and method forming same

Patent metadata

Field	Value
Publication number	US-10510598-B2
Application number	US-201615386952-A
Country	US
Kind code	B2
Filing date	Dec 21, 2016
Priority date	Nov 29, 2016
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A method includes forming a bottom source/drain contact plug in a bottom inter-layer dielectric. The bottom source/drain contact plug is electrically coupled to a source/drain region of a transistor. The method further includes forming an inter-layer dielectric overlying the bottom source/drain contact plug. A source/drain contact opening is formed in the inter-layer dielectric, with the bottom source/drain contact plug exposed through the source/drain contact opening. A dielectric spacer layer is formed to have a first portion extending into the source/drain contact opening and a second portion over the inter-layer dielectric. An anisotropic etching is performed on the dielectric spacer layer, and a remaining vertical portion of the dielectric spacer layer forms a source/drain contact spacer. The remaining portion of the source/drain contact opening is filled to form an upper source/drain contact plug.

First claim

What is claimed is:

1. A method comprising:
forming a first inter-layer dielectric overlying a source/drain region of a transistor;
forming a first source/drain contact opening in the first inter-layer dielectric;
forming a first source/drain contact spacer in the first source/drain contact opening;

filling a remaining portion of the first source/drain contact opening to form a first source/drain contact plug electrically coupling to the source/drain region;
forming a first etch stop layer over and in contact with the first inter-layer dielectric, a gate spacer of the transistor and the first source/drain contact plug;
forming a second inter-layer dielectric overlying and contacting the first etch stop layer;
forming a second source/drain contact plug in the second inter-layer dielectric, wherein the second source/drain contact plug is over and contacting the first source/drain contact plug;
forming a third inter-layer dielectric overlying the second inter-layer dielectric;
etching the second inter-layer dielectric and the third inter-layer dielectric to form a gate contact opening, with a gate electrode of the transistor exposed through the gate contact opening;
etching the third inter-layer dielectric, wherein a second source/drain contact opening is formed to reveal the second source/drain contact plug;
simultaneously forming a gate contact spacer and a source/drain contact spacer extending into the gate contact opening and the second source/drain contact opening, respectively, wherein the gate contact spacer comprises an edge contacting an edge of the gate spacer to form a vertical interface; and
filling remaining portions of the gate contact opening and the second source/drain contact opening simultaneously to form a gate contact plug and a third source/drain contact plug, respectively.

2. The method of claim 1 further comprising:
filling the gate contact opening with a patterned photo resist, wherein the patterned photo resist is used as an etching mask when third inter-layer dielectric is etched to form the second source/drain contact opening; and
removing the patterned photo resist before the gate contact plug and the third source/drain contact plug are formed.

3. The method of claim 1 further comprising:
forming a first low-k dielectric layer over the third inter-layer dielectric;
forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source/drain region; and
forming a dielectric metal line spacer encircling the metal line.

4. The method of claim 3 further comprising:
forming a second low-k dielectric layer over the first low-k dielectric layer;
forming a metal via in the second low-k dielectric layer, wherein the metal via is electrically coupled to the source/drain region; and
forming a dielectric via spacer encircling the metal via.

5. The method of claim 1 further comprising:
forming a sacrificial layer over a gate stack of the transistor;
etching the sacrificial layer and the first inter-layer dielectric to form the first source/drain contact opening that extends into the sacrificial layer, wherein the first source/drain contact spacer and the first source/drain contact plug are formed in the first source/drain contact opening and extending into the sacrificial layer; and
performing a planarization to remove the sacrificial layer and portions of the first source/drain contact spacer and the first source/drain contact plug in the sacrificial layer.

6. The method of claim 1 , wherein the gate contact spacer comprises a bottom surface contacting a top surface of a gate dielectric, wherein the gate dielectric contacts the gate spacer.

7. The method of claim 1 , wherein the gate contact spacer extends to a level lower than a top surface level of the first inter-layer dielectric.

8. The method of claim 1 further comprising etching a hard mask between the two gate spacers to extend the gate contact opening between the two gate spacers.

9. A method comprising:
forming a first source/drain contact plug in a first inter-layer dielectric, wherein the first source/drain contact plug is electrically coupled to a source/drain region of a transistor;
forming a second inter-layer dielectric overlying the first inter-layer dielectric;
forming a second source/drain contact plug in the second inter-layer dielectric;
forming a third inter-layer dielectric overlying the second inter-layer dielectric;
etching the second inter-layer dielectric and the third inter-layer dielectric to form a gate contact opening, wherein a gate electrode of the transistor is exposed to the gate contact opening;
after the second inter-layer dielectric and the third inter-layer dielectric are etched to form the gate contact opening, etching a hard mask between gate spacers of the transistor to extend the gate contact opening between the gate spacers;
filling the gate contact opening with a photo resist;
removing the photo resist from the gate contact opening;
forming a gate contact spacer in the gate contact opening, wherein the gate contact spacer penetrates through the second inter-layer dielectric and the third inter-layer dielectric; and
forming a gate contact plug in the gate contact opening, wherein the gate contact plug is encircled by the gate contact spacer.

10. The method of claim 9 further comprising:
etching the third inter-layer dielectric using the photo resist as an etching mask to form a source/drain contact opening, wherein the second source/drain contact plug is exposed through the source/drain contact opening;
forming a source/drain contact spacer in the source/drain contact opening; and
forming a third source/drain contact plug in the source/drain contact opening, wherein the second source/drain contact plug is encircled by the source/drain contact spacer.

11. The method of claim 10 , wherein the forming the gate contact spacer and the forming the source/drain contact spacer share a common deposition process and a common etching process.

12. The method of claim 9 , wherein the forming the gate contact spacer comprises:
depositing a dielectric spacer layer extending into the gate contact opening and penetrating through the second inter-layer dielectric and the third inter-layer dielectric; and
performing an anisotropic etching on the dielectric spacer layer, wherein a remaining portion of the dielectric spacer layer forms the gate contact spacer.

13. The method of claim 9 wherein the gate contact spacer and the gate contact plug extend to a level lower than top surfaces of the gate spacers.

14. The method of claim 9 further comprising:
forming a first low-k dielectric layer over the third inter-layer dielectric;
forming a metal line in the first low-k dielectric layer, wherein the metal line is electrically coupled to the source/drain region; and
forming a dielectric metal line spacer encircling the metal line.

15. The method of claim 14 further comprising:
forming a second low-k dielectric layer over the first low-k dielectric layer;
forming a via in the second low-k dielectric layer, wherein the via is electrically coupled to the source/drain region; and
forming a dielectric via spacer encircling the via.

16. A method comprising:
forming a replacement gate stack between two gate spacers, wherein the replacement gate stack and the two gate spacers are in a first Inter-Layer Dielectric (ILD);
forming a hard mask overlapping the replacement gate stack, wherein the hard mask is also between the two gate spacers;
forming a source/drain region on a side of the replacement gat

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsieh Yi-Tsang
• Chao Cha-Hsin
• Chiu Yi-Wei
• Hsu Li-Te
• Hsia Ying Ting

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title

• H10W20/075

  of multilayered thin functional dielectric layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title