Semiconductor device

Patent metadata

Field	Value
Publication number	US-2020043791-A1
Application number	US-201816116730-A
Country	US
Kind code	A1
Filing date	Aug 29, 2018
Priority date	Aug 3, 2018
Publication date	Feb 6, 2020
Grant date	—

Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first gate, a gate dielectric layer, a pair of second gates, a first spacer, and a second spacer. The first gate is disposed on a substrate. The gate dielectric layer is disposed between the first gate and the substrate. The pair of second gates are disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate. The first spacer is disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covers the top surface of the first gate. The second spacer is disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

First claim

1 . A semiconductor device, comprising:
a first gate disposed on a substrate; a gate dielectric layer disposed between the first gate and the substrate; a pair of second gates disposed on the substrate and respectively located at two sides of the first gate, wherein top surfaces of the pair of second gates are higher than a top surface of the first gate; a first spacer disposed on sidewalls of the pair of second gates protruding from the top surface of the first gate and covering the top surface of the first gate, wherein the first spacer is in contact with the entire top surface of the first gate; and a second spacer disposed between the gate dielectric layer and the pair of second gates, between the first gate and the pair of second gates, and between the first spacer and the pair of second gates.

2 . The semiconductor device of claim 1 , further comprising a third spacer disposed on sidewalls of the pair of second gates away from the first gate.

3 . The semiconductor device of claim 2 , wherein a material of the third spacer and a material of the first spacer are the same.

4 . The semiconductor device of claim 2 , further comprising a silicide layer disposed on the top surfaces of the pair of second gates.

5 . The semiconductor device of claim 4 , wherein the top surfaces of the pair of second gates are lower than a top surface of the second spacer, and the semiconductor device further comprises a fourth spacer disposed on the top surfaces of the pair of second gates and located on the second spacer, and the silicide layer is located on exposed portions of the top surfaces of the pair of second gates.

6 . The semiconductor device of claim 5 , wherein a material of the third spacer, a material of the fourth spacer, and a material of the first spacer are the same.

7 . The semiconductor device of claim 1 , wherein a material of the first spacer comprises a nitride.

8 . The semiconductor device of claim 1 , wherein a material of the second spacer comprises an oxide.

9 . The semiconductor device of claim 1 , wherein a ratio of a height of the pair of second gates protruding from the top surface of the first gate to a width of the first gate is greater than 2.

10 . A manufacturing method of a semiconductor device, comprising:
forming a gate structure on a substrate, wherein the gate structure comprises a gate dielectric layer located on the substrate, a first gate located on the gate dielectric layer, and a hard mask layer located on the first gate; forming a first spacer on sidewalls of the gate structure; forming a second gate on the first spacer respectively at two sides of the gate structure, wherein a top surface of the second gate is higher than a top surface of the first gate; removing the hard mask layer; and forming a second spacer on sidewalls of the first spacer protruding from the top surface of the first gate and on sidewalls of the second gate, wherein the second spacer covers the top surface of the first gate.

11 . The manufacturing method of the semiconductor device of claim 10 , wherein a forming method of the gate structure comprises:
forming a gate dielectric material layer, a gate material layer, and a hard mask material layer on the substrate in order; and performing a patterning process to remove a portion of the gate dielectric material layer, a portion of the gate material layer, and a portion of the hard mask material layer.

12 . The manufacturing method of the semiconductor device of claim 10 , wherein a forming method of the first spacer comprises:
conformally forming a spacer material layer on the substrate; and performing an anisotropic etching process to remove a portion of the spacer material layer and keep the spacer material layer located on the sidewalls of the gate structure.

13 . The manufacturing method of the semiconductor device of claim 10 , wherein a forming method of the second gate comprises:
conformally forming a gate material layer on the substrate; and performing an anisotropic etching process to remove a portion of the gate material layer and keep the gate material layer located on the sidewalls of the gate structure.

14 . The manufacturing method of the semiconductor device of claim 13 , wherein after the anisotropic etching process is performed, a top surface of the gate material layer located on the sidewalls of the gate structure is lower than a top surface of the hard mask layer.

15 . The manufacturing method of the semiconductor device of claim 10 , wherein a forming method of the second spacer comprises:
conformally forming a spacer material layer on the substrate; and performing an anisotropic etching process to remove a portion of the spacer material layer and keep the spacer material layer located on the sidewall of the first spacer, the top surface of the first gate, and the sidewalls of the second gate.

16 . The manufacturing method of the semiconductor device of claim 10 , further comprising forming a silicide layer on the top surface of the second gate.

17 . The manufacturing method of the semiconductor device of claim 10 , wherein a material of the first spacer comprises an oxide.

18 . The manufacturing method of the semiconductor device of claim 10 , wherein a material of the second spacer comprises a nitride.

19 . The manufacturing method of the semiconductor device of claim 10 , wherein a material of the hard mask layer comprises a nitride.

20 . The manufacturing method of the semiconductor device of claim 10 , wherein a ratio of a height of the hard mask layer to a width of the first gate is greater than 2.

Assignees

• United Microelectronics Corp

Inventors

• Liu wei-chang
• Chen Zhen
• Wang Shen-De
• Xiang Wang
• Ta Wei
• Fang Ling-Gang
• Xue Shang

Classifications

• H01L21/823443

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic

• H01L21/82345 Primary

  Electricity · mapped topic

• H01L27/088

  Electricity · mapped topic