Superconducting bump bonds
US-10497853-B2 · Dec 3, 2019 · US
Superconducting bump bonds
US2020006621A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2020006621-A1 |
| Application number | US-201916557412-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 30, 2019 |
| Priority date | Dec 15, 2015 |
| Publication date | Jan 2, 2020 |
| Grant date | — |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
First claim
Opening claim text (preview).
What is claimed is: 1 . A device comprising: a first chip comprising a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, wherein the barrier layer is titanium nitride; a superconducting bump bond on the barrier layer; and a second chip joined to the first chip by the superconducting bump bond, the second chip comprising a first quantum circuit element, wherein the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element. 2 . The device of claim 1 , wherein the first interconnect pad is aluminum. 3 . The device of claim 1 , wherein the superconducting bump bond is indium. 4 . The device of claim 1 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device. 5 . The device of claim 1 , wherein the first circuit element comprises a second quantum circuit element. 6 . The device of claim 1 , wherein at least one of the first chip and the second chip comprises a silicon substrate. 7 . The device of claim 1 , wherein at least one of the first chip and the second chip comprises a sapphire substrate. 8 . The device of claim 1 , wherein a first surface of the first chip is spaced apart from and faces a first surface of the second chip to form a gap.
Assignees
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Classifications
between stacked chips · CPC title
characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title
relative to the surface, e.g. recessed, protruding · CPC title
Compression bonding, e.g. thermocompression bonding · CPC title
Cleaning, e.g. oxide removal · CPC title
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- What does patent US2020006621A1 cover?
- A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the supercon…
- Who is the assignee on this patent?
- Google Llc
- What technology area does this patent fall under?
- Primary CPC classification H10N69/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jan 02 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).