Semiconductor device

Patent metadata

Field	Value
Publication number	US-9947670-B2
Application number	US-201514743500-A
Country	US
Kind code	B2
Filing date	Jun 18, 2015
Priority date	Sep 5, 2014
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first-conductivity-type semiconductor layer on a semiconductor substrate;
a first pillar-shaped semiconductor layer on the semiconductor substrate and including sequentially from the substrate, a first first-conductivity-type semiconductor layer in contact with the substrate, a first body region, a second first-conductivity-type semiconductor layer, the first pillar-shaped semiconductor layer further including sequentially above the second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer;
a first gate insulating film around the first body region;
a first gate around the first gate insulating film;
a second gate insulating film around the second body region;
a second gate around the second gate insulating film;
a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer;
a second pillar-shaped semiconductor layer on the semiconductor substrate and including sequentially from the substrate, a third first-conductivity-type semiconductor layer in contact with the substrate, a third body region, a fourth first-conductivity-type semiconductor layer, the second pillar-shaped semiconductor layer further including sequentially above the fourth first-conductivity-type semiconductor layer, a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-type semiconductor layer;
a third gate insulating film around the third body region;
a third gate around the third gate insulating film;
a fourth gate insulating film around the fourth body region;
a fourth gate around the fourth gate insulating film;
a second output terminal connected to the fourth first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer;
a third pillar-shaped semiconductor layer on the first output terminal and including sequentially from the first output terminal, a fifth first-conductivity-type semiconductor layer, a fifth body region, and a sixth first-conductivity-type semiconductor layer;
a fifth gate insulating film around the fifth body region;
a fifth gate around the fifth gate insulating film;
a fourth pillar-shaped semiconductor layer on the second output terminal and including sequentially from the second output terminal, a seventh first-conductivity-type semiconductor layer, a sixth body region, and an eighth first-conductivity-type semiconductor layer;
a sixth gate insulating film around the sixth body region; and
a sixth gate around the sixth gate insulating film,
wherein the fifth first-conductivity-type semiconductor layer is connected to the second output terminal,
the seventh first-conductivity-type semiconductor layer is connected to the first output terminal,
the first gate, the second gate, and the second output terminal are connected to one another, and
the third gate, the fourth gate, and the first output terminal are connected to one another.

2. The semiconductor device according to claim 1 , further comprising:
a first contact that connects the first gate, the second gate, and the second output terminal to one another; and
a second contact that connects the third gate, the fourth gate, and the first output terminal to one another.

3. The semiconductor device according to claim 1 , further comprising:
a first connecting region between the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; and
a second connecting region between the fourth first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

5. The semiconductor device according to claim 1 , wherein the first output terminal and the second output terminal are composed of a metal.

6. The semiconductor device according to claim 1 , wherein the first output terminal and the second output terminal are composed of a semiconductor.

7. The semiconductor device according to claim 1 , wherein the first gate, the second gate, the third gate, the fourth gate, the fifth gate, and the sixth gate are composed of a metal.

8. The semiconductor device according to claim 1 , further comprising:
a first power supply line connected to the second second-conductivity-type semiconductor layer;
a second power supply line connected to the fourth second-conductivity-type semiconductor layer;
a first bit line connected to the sixth first-conductivity-type semiconductor layer; and
a second bit line connected to the eighth first-conductivity-type semiconductor layer.

9. The semiconductor device according to claim 1 , wherein the first pillar-shaped semiconductor layer is disposed in a first column of a first row, the second pillar-shaped semiconductor layer is disposed in a second column of a second row, the third pillar-shaped semiconductor layer is disposed in the second column of the first row, and the fourth pillar-shaped semiconductor layer is disposed in the first column of the second row.

Assignees

• Unisantis Elect Singapore Pte

Inventors

• Masuoka Fujio
• Nakamura Hiroki

Classifications

• H01L27/0688

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H01L27/1104 Primary

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title