Integrated mult-die partitioned voltage regulator

Patent metadata

Field	Value
Publication number	US-2020006292-A1
Application number	US-201816022515-A
Country	US
Kind code	A1
Filing date	Jun 28, 2018
Priority date	Jun 28, 2018
Publication date	Jan 2, 2020
Grant date	—

Abstract

A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

First claim

we claim:

1 . A semiconductor package comprising:
a first die comprising a first section of a power converter; and a second die comprising a second section of the power converter, wherein the power converter comprises: a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches, wherein the PM circuitry comprises a first part and a second part, wherein the first section of the power converter in the first die includes the first part of the PM circuitry, and wherein the second section of the power converter in the second die includes the second part of the PM circuitry.

2 . The semiconductor package of claim 1 , wherein the PM circuitry comprises:
a plurality of sense circuitries, wherein an individual sense circuitry of the plurality of sense circuitries is to sense one or both of a voltage or a current of a corresponding switch of the plurality of switches, wherein the first part of the PM circuitry in the first die includes a first subset of the plurality of sense circuitries, and, wherein the second part of the PM circuitry in the second die includes a second subset of the plurality of sense circuitries.

3 . The semiconductor package of claim 1 , wherein the PM circuitry comprises:
a controller; and a sense circuitry to sense a parameter of a corresponding switch, and transmit the sensed parameter to the controller, wherein the first part of the PM circuitry in the first die includes a first portion of the sense circuitry, which is to sense the parameter of the switch, and wherein the second part of the PM circuitry in the second die includes a second portion of the sense circuitry, which is to transmit the sensed parameter to the controller.

4 . The semiconductor package of claim 3 , wherein the second part of the sense circuitry comprises an analog to digital converter (ADC) to digitalize the sensed parameter for transmission to the controller.

5 . The semiconductor package of claim 1 , wherein:
the first section of the power converter in the first die includes a first subset of the plurality of switches; and the second section of the power converter in the second die includes a second subset of the plurality of switches.

6 . The semiconductor package of claim 1 , wherein the PM circuitry comprises:
a plurality of driver circuitries, wherein an individual driver circuitry of the plurality of driver circuitries is to drive a corresponding switch of the plurality of switches, wherein the first section of the power converter in the first die includes a first subset of the plurality of driver circuitries, and wherein the second section of the power converter in the second die includes a second subset of the plurality of driver circuitries.

7 . The semiconductor package of claim 1 , comprising:
a substrate, wherein at least one of the first or second dies is on the substrate, wherein the power converter comprises a plurality of passive components, and wherein one or more of the plurality of passive components are on, or embedded within, the substrate.

8 . The semiconductor package of claim 1 , wherein the PM circuitry comprises:
a controller; and a feedback circuitry to measure an output voltage of the power converter, and transmit the measured voltage to the controller, wherein the first part of the PM circuitry in the first die includes a first portion of the feedback circuitry, which is to measure the output voltage; and wherein the second part of the PM circuitry in the second die includes a second portion of the feedback circuitry, which is to digitalize the measurement of the output voltage and transmit the digitalized measurement of the output voltage to the controller.

9 . The semiconductor package of claim 1 , wherein the PM circuitry comprises:
a plurality of analog components; and a plurality of digital components, wherein the first part of the PM circuitry in the first die includes the plurality of analog components; and wherein the second part of the PM circuitry in the second die includes the plurality of digital components.

10 . The semiconductor package of claim 1 , further comprising:
a substrate, wherein one or more passive components of the power converter are on, or embedded within, the substrate, wherein the substrate has a first side and a second side that is opposite the first side, wherein the substrate has a recess on the second side, wherein the first die is on the first side of the substrate, and wherein the second die is at least in part within the recess on the second side of the substrate.

11 . The semiconductor package of claim 10 , wherein:
the recess is a first recess; the substrate has a second recess on the first side, wherein the first die is at least in part within the second recess on the first side of the substrate.

12 . The semiconductor package of claim 1 , further comprising:
a substrate, wherein one or more passive components of the power converter are on, or embedded within, the substrate, wherein the first die is on the substrate, and wherein the second die is stacked on the first die.

13 . The semiconductor package of claim 12 , wherein:
the substrate has a recess, such that the first die is at least in part within the recess.

14 . The semiconductor package of claim 1 , wherein the power converter is a first power converter, and wherein the semiconductor package further comprises:
a third die comprising a first section of a second power converter, wherein one of the first die or the second die comprises a second section of the second power converter.

15 . A system comprising:
a first die comprising one or more of: a memory to store instructions, a processor to execute the instructions, or a wireless interface to facilitate communication between the processor and another system, the first die further comprising a first section of a Voltage Regulator (VR); and a second die comprising a second section of the VR, wherein the VR comprises: a plurality of switches, and a Power Management (PM) circuitry to control operation of the VR by controlling switching of the plurality of switches, wherein the PM circuitry comprises a first part and a second part, wherein the first section of the VR in the first die includes the first part of the PM circuitry, and wherein the second section of the VR in the second die includes the second part of the PM circuitry.

16 . The system of claim 15 , further comprising:
a power supply to supply power to the system; and a substrate comprising one or more passive components of the VR, wherein at least one of the first or second dies is on the substrate.

17 . A Voltage Regulator (VR) comprising:
a passive component; first and second switches coupled to a first terminal of the passive component; third and fourth switches coupled to a second terminal of the passive component; first, second, third and fourth drivers to respectively control switching of the first, second, third and fourth switches, wherein the first switch, the second switch, the first driver, and the second driver are included in a first die, wherein the third switch, the fourth switch, the third driver, and the fourth driver are included in a second die, and wherein the passive component is external to the first and second dies.

18 . The VR of claim 17 , wherein the passive components is at least one of a capacitor or an inductor that is on a substrate, and wherein at least one of the firs

Assignees

• Intel Corp

Inventors

• Choi Beomseok
• Kulasekaran Siddharth
• Radhakrishnan Kaladhar

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title