Passive components in vias in a stacked integrated circuit package

Patent metadata

Field	Value
Publication number	US-10236209-B2
Application number	US-201414583015-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Mar 19, 2019
Grant date	Mar 19, 2019

Abstract

Integrated passive component in a stacked integrated circuit package are described. In one embodiment an apparatus has a substrate, a first die coupled to the substrate over the substrate, the first die molding a power supply circuit coupled to the substrate to receive power, a second die having a processing core and coupled to the first die over the first die, the first die being coupled to the power supply circuit to power the processing core, a via through the first die, and a passive device formed in the via of the first die and coupled to the power supply circuit.

First claim

The invention claimed is:

1. An apparatus comprising:
a substrate;
a first die coupled to the substrate over the substrate, the first die having a front side including circuitry facing the substrate and a back side, the first die including a power supply circuit coupled to the substrate to receive power;
an inductor positioned in a recess on the back side of the first die, the recess not extending through the first die, and the recess having a bottom surface and sidewalls angled less than 90 degrees from the bottom surface, wherein the inductor comprises a magnetic material, wherein the magnetic material of the inductor is on the bottom surface of the recess and on the angled sidewalls of the recess, and wherein a copper winding is completely embedded within the magnetic material;
a capacitor embedded in the back side of the first die and coupled to the inductor through a redistribution layer on the back side of the first die and to the power supply circuit through a through-silicon via to form an LC filter;
a second die having a processing core and coupled to the first die over the back side of the first die, the second die being coupled to the power supply circuit through the LC filter to power the processing core.

2. The apparatus of claim 1 , wherein the front side of the first die is coupled to the second die using additional through-silicon coupling vias through the first die.

3. The apparatus of claim 1 , wherein the back side of the first die is coupled to the substrate using bonding wires.

4. The apparatus of claim 1 , wherein the capacitor comprises a high k dielectric material lining and an electrode on the high k dielectric material lining.

5. The apparatus of claim 1 , wherein the inductor comprises is formed by a magnetic inductor material lining the recess and an electrode within the magnetic inductor material lining.

6. The apparatus of claim 1 , further comprising further capacitors coupled to further inductors, the capacitors and the inductors being formed in vias of the first die.

7. The apparatus of claim 1 , wherein the first die is a silicon die and wherein the capacitor is a metal-insulator-metal capacitor.

8. The apparatus of claim 6 , wherein the further inductors comprise magnetic core inductors, stripe inductors, spiral inductors, solenoid inductors or torus inductors.

9. The apparatus of claim 8 , wherein the power supply circuit comprises either a voltage converter, a switched capacitor voltage converter, a voltage regulator or a fully integrated voltage regulator.

10. The apparatus of claim 1 , further comprising a molding compound over the first and second die to physically isolate and protect the dies.

11. A stacked die package comprising:
a cores die having a plurality of processing cores;
an uncore die having a back side facing the cores die and a front side, the uncore die having a power supply circuit on the front side for each processing core, each power supply circuit being independently coupled to each respective processing core to supply power to the respective processing core;
a package substrate coupled to the uncore die so that the front side is facing the package substrate to receive power from an external source and to provide power to the power supply circuits of the uncore die;
a plurality of through-silicon vias through the uncore die to carry data signals from the cores die to the package substrate; and
a plurality of recesses in the back side of the uncore die, the recesses not through the back side of the uncore die in which inductors are formed, and the recesses each having a bottom surface and sidewalls angled less than 90 degrees from the bottom surface, wherein each of the inductors comprises a magnetic material, wherein the magnetic material of each inductor is on the bottom surface and on the angled sidewalls of a corresponding one of the recesses, and wherein a copper winding is completely embedded within the magnetic material of each of the inductors;
a plurality of capacitors embedded in the backside of the uncore die, the capacitors being coupled to the inductors through a redistribution layer on the back side of the die to form an LC filter for each processing core, the power supply circuit for each processing core being coupled to the respective processing core through a through-silicon via to the respective LC filter.

12. The stacked die package of claim 11 , wherein the plurality of capacitors comprise a dielectric lining and an electrode on the dielectric lining.

13. A computing device comprising:
a system board;
a communication package connected to the system board; and
a processor package having a substrate, an uncore die coupled to the substrate over the substrate, the uncore die having a front side including circuitry facing the substrate and a back side, the uncore die including a power supply circuit coupled to the substrate to receive power, a cores die having a processing core and coupled to the uncore die over the back side of the uncore die, the uncore die being coupled to the power supply circuit to power the processing core, a via through the uncore die, an inductor positioned in a recess in the backside of the uncore die, the recess not through the uncore die, and the recess having a bottom surface and sidewalls angled less than 90 degrees from the bottom surface, wherein the inductor comprises a magnetic material, wherein the magnetic material of the inductor is on the bottom surface of the recess and on the angled sidewalls of the recess, and wherein a copper winding is completely embedded within the magnetic material, the processor package further comprising a capacitor embedded in the backside of the uncore die and coupled to the inductor through a redistribution layer on the back side of the undore die to form an LC filter wherein the processing core is coupled to the power supply circuit ofthe uncore die through a through-silicon via to the LC filter.

14. An apparatus comprising:
a substrate;
a first die coupled to the substrate over the substrate, the first die having a front side including circuitry facing the substrate and a back side, the first die including a power supply circuit coupled to the substrate to receive power;
a molding compound over the first die to physically isolate and protect the first die during thinning;
a second die having a processing core and coupled to the first die over the back side of the first die and over the molding compound, the second die being coupled to the power supply circuit of the first die to power the processing core; and
an inductor in a recess in formed within a via on the back side of the first die, the recess not extending through the first die, and the recess having a bottom surface and sidewalls angled less than 90 degrees from the bottom surface, wherein the inductor comprises a magnetic material, wherein the magnetic material of the inductor is on the bottom surface of the recess and on the angled sidewalls of the recess, and wherein a copper winding is completely embedded within the magnetic material;
a capacitor embedded in the back side of the first die, the capacitor coupled to the inductor through a redistribution layer on the back side of the first die to form an LC filter, and wherein the processing core of the second die is coupled to the power supply circuit through a through-silicon via to the LC filter.

15. The apparatus of claim 14 , further comprising a plurality of passive devices formed on a surface of the first die and coupled to the inductor and to the power supply circuit.

16. The apparatus of claim 14 , wherein the front side of the

Assignees

• Intel Corp

Inventors

• Sharan Sujit
• Mahajan Ravindranath
• Rusu Stefan
• Gardner Donald S

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title