Semiconductor chip power supply system

US10873262B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10873262-B2
Application numberUS-202016808662-A
CountryUS
Kind codeB2
Filing dateMar 4, 2020
Priority dateSep 7, 2017
Publication dateDec 22, 2020
Grant dateDec 22, 2020

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides a semiconductor chip power supply system, including: a semiconductor chip including: a first data processing function area and a first power converter control area, the first data processing function area and the first power converter control area being formed on a first semiconductor substrate of the semiconductor chip; and a first power converter power stage located outside the first semiconductor substrate and electrically connected to the first power converter control area and the first data processing function area; wherein the first power converter control area controls the first power converter power stage to supply power to the first data processing function area.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor chip power supply system, comprising: a semiconductor chip comprising: a first data processing function area and a first power converter control area, the first data processing function area and the first power converter control area being formed on a first semiconductor substrate of the semiconductor chip; and a first power converter power stage located outside the first semiconductor substrate and electrically connected to the first power converter control area and the first data processing function area; wherein the first power converter control area controls the first power converter power stage to supply power to the first data processing function area, and the first power converter control area receives a signal of an output voltage of the first power converter power stage and adjusts an output voltage of the first power converter power stage according to a working frequency of the first data processing function area; wherein the first power converter power stage comprises: at least a switch, a driver and at least a passive device. 2. The semiconductor chip power supply system according to claim 1 , wherein the semiconductor chip comprises: a drive signal sending pin, the first power converter control area sends a drive signal to the driver via the drive signal sending pin, the driver drives the switch according to the drive signal, and the switch cooperates with the passive device to supply power to the first data processing function area. 3. The semiconductor chip power supply system according to claim 1 , wherein the first power converter power stage comprises: a multi-phase paralleled buck circuit or a switched capacitor circuit. 4. The semiconductor chip power supply system according to claim 2 , wherein the first power converter power stage comprises: a working status signal sending pin for sending a working status signal of the first power converter power stage to the first power converter control area, and the semiconductor chip comprises: a working status signal receiving pin for receiving the working status signal and transmitting the working status signal to the first power converter control area inside the semiconductor chip. 5. The semiconductor chip power supply system according to claim 4 , wherein the drive signal sending pin and the working status signal receiving pin are multiplexed. 6. The semiconductor chip power supply system according to claim 1 , wherein the semiconductor chip comprises: a first power supply pin and a second power supply pin, the first power supply pin is electrically connected to the first data processing function area and receives a first voltage provided by the first power converter power stage to supply power to the first data processing function area, and the second power supply pin is electrically connected to the first power converter control area and receives a second voltage to supply power to the first power converter control area. 7. The semiconductor chip power supply system according to claim 6 , wherein the first power supply pin is further electrically connected to the first power converter control area, and when the first voltage is greater than a threshold value, the first voltage of the first power supply pin is used to supply power to the first power converter control area instead of the second voltage of the second power supply pin. 8. The semiconductor chip power supply system according to claim 1 , wherein the semiconductor chip further comprises: a first power management data register and a first semiconductor chip power management area, the first power management data register is electrically connected to the first semiconductor chip power management area, the first power management data register is electrically connected to the first power converter control area, the first semiconductor chip power management area provides a control parameter required by the first power converter control area and stores the control parameter into the first power management data register, and the first power converter control area adjusts a power output of the first power converter power stage by reading the control parameter in the first power management data register. 9. The semiconductor chip power supply system according to claim 1 , wherein the number of the first data processing function areas is N, and each of the first data processing function areas is electrically connected to the first power supply pin, N being greater than or equal to 2. 10. The semiconductor chip power supply system according to claim 6 , wherein the semiconductor chip further comprises: a second data processing function area and a second power converter control area, the second data processing function area and the second power converter control area are formed on the first semiconductor substrate of the semiconductor chip; and the semiconductor chip power supply system further comprises: a second power converter power stage located outside the first semiconductor substrate and electrically connected to the second power converter control area and the second data processing function area; wherein the second power converter control area controls the second power converter power stage to supply power to the second data processing function area. 11. The semiconductor chip power supply system according to claim 10 , wherein the semiconductor chip comprises: a third power supply pin and a fourth power supply pin, the third power supply pin is electrically connected to the second data processing function area and receives a third voltage provided by the second power converter power stage to supply power to the second data processing function area, and the fourth power supply pin is electrically connected to the second power converter control area and receives a fourth voltage to supply power to the second power converter control area. 12. The semiconductor chip power supply system according to claim 11 , wherein the first voltage is different from the third voltage, or the second voltage is different from the fourth voltage, or the first voltage is different from the third voltage and the second voltage is different from the fourth voltage. 13. The semiconductor chip power supply system according to claim 10 , wherein the semiconductor chip comprises: a third power supply pin, the third power supply pin is electrically connected to the second data processing function area and receives a third voltage provided by the second power converter power stage to supply power to the second data processing function area, and the second power supply pin is further electrically connected to the second power converter control area to supply power to the second power converter control area. 14. The semiconductor chip power supply system according to claim 10 , wherein the semiconductor chip further comprises: a second power management data register and a second semiconductor chip power management area, the second power management data register is electrically connected to the second semiconductor chip power management area, the second power management data register is electrically connected to the second power converter control area, the second semiconductor chip power management area provides a control parameter required by the second power converter control area and stores the control parameter into the second power management data register, and the second power converter control area adjusts a power output of the second power converter power stage by reading the control parameter in the second power management data register. 15. The semiconductor chip power supply system according to

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • H02M3/1584Primary

    with a plurality of power processing stages connected in parallel · CPC title

  • H02M3/1588Primary

    comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

  • Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

  • Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

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What does patent US10873262B2 cover?
The present disclosure provides a semiconductor chip power supply system, including: a semiconductor chip including: a first data processing function area and a first power converter control area, the first data processing function area and the first power converter control area being formed on a first semiconductor substrate of the semiconductor chip; and a first power converter power stage lo…
Who is the assignee on this patent?
Delta Electronics Shanghai Co
What technology area does this patent fall under?
Primary CPC classification H02M3/1584. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 22 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).