Methods of forming semiconductor devices having threshold switching devices

Patent metadata

Field	Value
Publication number	US-2019355905-A1
Application number	US-201916529017-A
Country	US
Kind code	A1
Filing date	Aug 1, 2019
Priority date	Aug 3, 2016
Publication date	Nov 21, 2019
Grant date	—

Abstract

Forming a semiconductor device that includes a memory cell array may include performing a switching firing operation on one or more memory cells of the memory array to cause a threshold voltage distribution associated with threshold switching devices in the memory cells to be reduced. The switching device firing operation may be performed such that the threshold voltage distribution is reduced while maintaining the one or more threshold switching devices in the amorphous state. Performing the switching device firing operation on a threshold switching device may include heating the threshold switching device, applying a voltage to the threshold switching device, applying a current to the threshold switching device, some combination thereof, or the like.

First claim

What is claimed is:

1 . A method, comprising:
forming a memory cell array on a semiconductor substrate, the memory cell array including,
a set of first conductive lines,
a set of second conductive lines extending substantially perpendicularly to the first conductive lines, and
a set of memory cells between the first conductive lines and the second conductive lines, the memory cells including data storage elements and threshold switching devices in an amorphous phase, each threshold switching device configured to change resistance based on a magnitude of a voltage applied on the threshold switching device at least meeting a threshold voltage associated with the threshold switching device, respectively; and
performing a switching device firing operation on the memory cell array while maintaining the threshold switching devices in an amorphous state, such that a threshold voltage distribution associated with the threshold switching devices is reduced.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Min Kyu
• Park Seong Geon
• Seong Dong Jun
• Ahn Dong Ho
• Lee Jung Moo
• Choi Seol
• Horn Hideki

Classifications

• G11C2013/0083

  Write to perform initialising, forming process, electro forming or conditioning · CPC title

• G11C13/0021

  Auxiliary circuits · CPC title

• G11C2213/76

  Array using an access device for each cell which being not a transistor and not a diode · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C13/0002 Primary

  using resistive RAM [RRAM] elements · CPC title