Semiconductor Device with Copper Structure

US2019304884A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019304884-A1
Application numberUS-201916368064-A
CountryUS
Kind codeA1
Filing dateMar 28, 2019
Priority dateMar 29, 2018
Publication dateOct 3, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.

First claim

Opening claim text (preview).

What is claimed is: 1 . A semiconductor device, comprising: a semiconductor body; a copper structure comprising a wiring/pad structure formed on the semiconductor body, wherein the wiring/pad structure comprises a top surface and a side surface; and a copper oxide layer on the top surface and on the side surface of the wiring/pad structure, wherein, in the copper oxide layer, a content of copper is between 60 at % and 75 at %, and a content of oxygen is between 25 at % and 40 at %. 2 . The semiconductor device of claim 1 , wherein, in the copper oxide layer, a content of cuprous oxide is at least 90%. 3 . The semiconductor device of claim 1 , wherein a thickness of the copper oxide layer is at least 50 nm. 4 . The semiconductor device of claim 1 , further comprising: an interlayer dielectric between the wiring/pad structure and the semiconductor body. 5 . The semiconductor device of claim 1 , wherein the copper structure comprises a bond wire electrically connecting the wiring/pad structure with a lead, and wherein the copper oxide layer is further formed on the bond wire. 6 . The semiconductor device of claim 5 , wherein the bond wire comprises a wire end in contact with the wiring/pad structure, and wherein the copper oxide layer is formed in a bonding area of the wiring/pad structure around the wire end. 7 . The semiconductor device of claim 5 , wherein the lead comprises copper and the copper oxide layer is further formed on at least a first portion of the lead. 8 . The semiconductor device of claim 1 , further comprising: a dielectric structure directly on the copper oxide layer, the dielectric structure comprising at least one of a reducing agent and an agent capable of forming a hydrogen-complex. 9 . The semiconductor device of claim 8 , wherein the dielectric structure comprises anticorrosion pigments. 10 . The semiconductor device of claim 8 , wherein the dielectric structure comprises polyimide and/or an epoxy resin. 11 . The semiconductor device of claim 1 , further comprising: a transistor cell formed in the semiconductor body, wherein the transistor cell is electrically connected to the copper structure. 12 . The semiconductor device of claim 1 , wherein: the semiconductor body comprises source regions, drain regions, a channel layer, and a supply layer, and the copper structure includes source electrodes and drain electrodes, the source electrodes are electrically connected to the source regions, the drain electrodes are electrically connected to the drain regions, the source regions and the channel layer form ohmic contacts, the drain regions and the channel layer form ohmic contacts, and the channel layer and the supply layer form a heterojunction. 13 . A semiconductor device, comprising: a semiconductor body; a copper structure comprising a wiring/pad structure formed on the semiconductor body, wherein the wiring/pad structure comprises a top surface and a side surface; and a copper oxide layer on the top surface and on the side surface of the wiring/pad structure, wherein the copper oxide layer comprises cuprous oxide. 14 . The semiconductor device of claim 13 , wherein the cuprous oxide is in direct contact with the copper structure. 15 . The semiconductor device of claim 13 , further comprising: a dielectric structure directly on the copper oxide layer, the dielectric structure comprising at least one of a reducing agent and an agent capable of forming a hydrogen-complex. 16 . A method of manufacturing a semiconductor device, the method comprising: forming, by electrochemical deposition, a copper oxide layer on a bond wire, wherein the bond wire comprises copper and electrically connects a semiconductor die with a lead frame; and forming a mold encapsulating the semiconductor die and the bond wire. 17 . The method of claim 16 , wherein the mold comprises at least one of a reducing agent and an agent capable of forming a hydrogen-complex. 18 . The method of claim 16 , wherein, in the copper oxide layer, a content of copper is between 60 at % and 75 at %, and a content of oxygen is between 25 at % and 40 at %. 19 . The method of claim 16 , wherein the lead frame comprises copper and the copper oxide layer is formed at least on a first portion of the lead frame. 20 . A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor body; forming a copper structure comprising a wiring/pad structure on the semiconductor body, wherein the wiring/pad structure comprises a top surface and a side surface; and forming a copper oxide layer directly on the copper structure, wherein the copper oxide layer is formed on the top surface and the side surface and wherein, in the copper oxide layer, a content of copper is between 60 at % and 75 at %, and a content of oxygen is between 25 at % and 40 at %. 21 . The method of claim 20 , wherein forming the copper oxide layer comprises electrochemical deposition. 22 . The method of claim 21 , wherein the electrochemical deposition uses an electric potential applied between the copper structure and an aqueous solution including copper ions. 23 . The method of claim 21 , wherein the electrochemical deposition comprises an electroless deposition of cuprous oxide. 24 . The method of claim 20 , further comprising: forming, prior to forming the copper structure, a transistor cell in the semiconductor body, wherein the copper structure is electrically connected to the transistor cell. 25 . A method of manufacturing a semiconductor device, the method comprising: providing a semiconductor body; providing a copper structure comprising a wiring/pad structure on the semiconductor body; and forming a copper oxide layer directly on the copper structure by electroless chemical plating. 26 . The method of claim 25 , wherein, in the copper oxide layer, a content of copper is between 60 at % and 75 at %, and a content of oxygen is between 25 at % and 40 at %. 27 . The method of claim 26 , wherein, in the copper oxide layer, a content of cuprous oxide is greater than 90%. 28 . The method of claim 25 , wherein forming the copper oxide layer comprises applying a solution that comprises copper(II) sulfate, lactic acid, and Na(OH).

Assignees

Inventors

Classifications

  • being rectangular · CPC title

  • Die-attach connectors and bond wires · CPC title

  • multiple bond wires connected to common bond pads at both ends of the wires · CPC title

  • Materials of bond wires · CPC title

  • changes in materials · CPC title

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What does patent US2019304884A1 cover?
A semiconductor device includes a copper structure over a semiconductor body. In a copper oxide layer on a surface of the copper structure, a content of copper is between 60 at % and 75 at % and a content of oxygen is between 25 at % and 40 at %.
Who is the assignee on this patent?
Infineon Technologies Austria Ag
What technology area does this patent fall under?
Primary CPC classification H10W70/481. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Oct 03 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).