Cache flush based on idle prediction and probe activity level

Patent metadata

Field	Value
Publication number	US-9021209-B2
Application number	US-70208510-A
Country	US
Kind code	B2
Filing date	Feb 8, 2010
Priority date	Nov 6, 2009
Publication date	Apr 28, 2015
Grant date	Apr 28, 2015

Abstract

A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.

First claim

What is claimed is:

1. A method comprising:
tracking probe activity level in a low-performance state processing node utilizing a probe counter with different increment and decrement values;
setting the processing node to a performance biased setting by setting the increment value higher than the decrement value;
predicting an idle duration of the processing node, wherein predicting the idle duration comprises satisfying at least two different idle predictions based on two or more of input/output activity, timers, interrupt rate tracking, and power state monitors;
comparing the probe activity level to a probe activity level threshold; and
flushing a cache memory in the low-performance state processing node if the probe activity level for the cache memory in the low-performance state processing node is above the probe activity level threshold and the predicted idle duration of the processing node is greater than an idle threshold.

2. The method as recited in claim 1 wherein flushing the cache memory further comprises write-back of valid cache data and invalidating the cache.

3. The method as recited in claim 1 further comprising applying a power savings voltage to the processing node.

4. The method as recited in claim 1 further comprising stopping probing the cache memory of the processing node.

5. The method as recited in claim 1 further comprising, if the predicted idle duration is below the idle duration threshold, and if the probe activity level is above the probe activity level threshold, increasing a performance state of the processing node to a first performance state higher than a current performance state.

6. The method as recited in claim 1 further comprising predicting the idle duration according to a frequency of received interrupts.

7. The method as recited in claim 1 further comprising predicting the idle duration according to a power state monitor monitoring duration of the processing node in a particular power state.

8. A processing system comprising:
a cache memory in a processing node;
a probe tracker to track probe activity level associated with the cache memory while the processing node is in a low performance state, the probe tracker including a counter having different increment and decrement values, wherein the counter is incremented by the increment value in response to a new probe request and the counter is decremented by the decrement value to reflect servicing of probe requests, wherein the increment value is set lower than the decrement value to set the processing node to a power savings biased setting; and
control functionality to flush the cache memory in response to the probe activity level being above a probe activity level threshold and at least one predicted idle duration of the processing node being greater than at least one threshold idle duration, wherein the probe activity level threshold is non-zero.

9. The processing system as recited in claim 8 wherein the processing system is responsive to the predicted idle duration being below the threshold idle duration and the probe activity level being above the probe activity level threshold, to increase a current performance state of the processing node to a first performance state higher than the current performance state.

10. The processing system as recited in claim 8 further comprising idle duration logic responsive to generate multiple idle duration predictions based on multiple ones of I/O activity, timer-tick activity, frequency of received interrupts, and a power state monitor, and to compare multiple idle duration predictions to a threshold idle duration to determine if idleness criteria is satisfied to flush the cache memory.

11. The processing system as recited in claim 8 wherein the threshold idle duration is programmable.

12. The processing system as recited in claim 8 wherein a plurality of idle duration predictions are utilized to determine whether to flush the cache memory.

13. The processing system as recited in claim 8 wherein the idle duration is predicted according to a rate of received interrupts.

14. The processing system as recited in claim 8 wherein the idle duration is predicted according to one or more power state monitors.

15. The processing system as recited in claim 8 wherein the idle duration is predicted according to input/output activity.

16. The processing system as recited in claim 8 wherein the probe tracker further comprises:
a low pass filter to filter out bursts of probing activity, the low pass filter supplying filtered probing requests to the counter.

17. The processing system as recited in claim 8 wherein the counter is decremented in response to a configurable time interval to reflect servicing of probe requests.

18. The processing system as recited in claim 17 wherein the decrement value matches a probing rate associated with a performance state of the processing node to reflect servicing of probe requests.

19. A method comprising:
tracking probe activity level in a low-performance state processing node, wherein tracking probe activity level comprises utilizing a probe counter with different increment and decrement values;
predicting the idle duration of the processing node, wherein predicting the idle duration comprises satisfying at least two different idle predictions based on two or more of input/output activity, timers, interrupt rate tracking, and power state monitors;
comparing the probe activity level to a probe activity level threshold;
flushing a cache memory in the low-performance state processing node if the probe activity level for the cache memory in the low-performance state processing node is above a probe activity level threshold and a predicted idle duration of the processing node is greater than an idle threshold; and
setting the processing node to a power savings biased setting by setting the increment value lower than the decrement value.

20. A processing system comprising:
a cache memory in a processing node;
a probe tracker to track probe activity level associated with the cache memory while the processing node is in a low performance state, the probe tracker including a counter having different increment and decrement values, wherein the counter is incremented by the increment value in response to a new probe request and the counter is decremented by the decrement value to reflect servicing of probe requests, wherein the increment value is set higher than the decrement value to set the processing node to a performance biased setting; and
control functionality to flush the cache memory in response to the probe activity level being above a probe activity level threshold and at least one predicted idle duration of the processing node being greater than at least one threshold idle duration, wherein the probe activity level threshold is non-zero.

Assignees

• Branover Alexander
• Steinman Maurice B
• Advanced Micro Devices Inc

Inventors

• Branover Alexander
• Steinman Maurice B

Classifications

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F1/32 Primary

  Means for saving power · CPC title