OPTIMAL FAULT-TOLERANT IMPLEMENTATIONS OF HEISENBERG INTERACTIONS AND CONTROLLED-Zª GATES

Patent metadata

Field	Value
Publication number	US-2019258757-A1
Application number	US-201916275030-A
Country	US
Kind code	A1
Filing date	Feb 13, 2019
Priority date	Feb 20, 2018
Publication date	Aug 22, 2019
Grant date	—

Abstract

The disclosure describes various aspects of techniques for optimal fault-tolerant implementations of controlled-Za gates and Heisenberg interactions. Improvements in the implementation of the controlled-Za gate can be made by using a clean ancilla and in-circuit measurement. Various examples are described that depend on whether the implementation is with or without measurement and feedforward. The implementation of the Heisenberg interaction can leverage the improved controlled-Za gate implementation. These implementations can cut down significantly the implementation costs associated with fault-tolerant quantum computing systems.

First claim

What is claimed is:

1 . A method for performing a quantum algorithm, comprising:
identifying use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1]; implementing the controlled-Z a gate for a fault-tolerant quantum information processing (QIP) system, wherein the implementation of the controlled-Z a gate includes multiple elements with only six (6) of the elements being controlled-NOT (CNOT) gates; mapping the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and performing the quantum algorithm based at least in part on the physical representation.

2 . The method of claim 1 , wherein the quantum algorithm is a quantum Fourier transform (QFT).

3 . The method of claim 1 , wherein implementing the controlled-Z a gate for the fault-tolerant QIP system includes identifying that the implementation of the controlled-Z a gate is without measurement and feedforward.

4 . The method of claim 1 , wherein the multiple elements of the implementation of the controlled-Z a gate further include:
one (1) parametrized Z a gate, eight (8) T gates, four (4) Hadamard (H) gates, and one (1) ancilla.

5 . The method of claim 1 , wherein implementing the controlled-Z a gate includes implementing the controlled-Z a gate without P gates and without P † gates.

6 . The method of claim 1 , wherein:
the fault-tolerant QIP system is a trapped-ion QIP system, and mapping the implementation of the controlled-Z a gate includes mapping the implementation of the controlled-Z a gate using multiple trapped-ion-based qubits in the trapped-ion QIP system.

7 . The method of claim 1 , wherein:
the fault-tolerant QIP system is a superconducting QIP system, and mapping the implementation of the controlled-Z a gate includes mapping the implementation of the controlled-Z a gate using multiple superconducting-based qubits in the superconducting QIP system.

8 . A fault-tolerant quantum information processing (QIP) system for performing a quantum algorithm, comprising:
an implementation component configured to:
identify use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1],
implement the controlled-Z a gate for the fault-tolerant QIP system, wherein the implementation of the controlled-Z a gate includes multiple elements with only six (6) of the elements being controlled-NOT (CNOT) gates, and
map the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and
an algorithms component configured to perform the quantum algorithm based at least in part on the physical representation.

9 . A non-transitory computer-readable medium storing code with instructions executable by a processor for performing a quantum algorithm, comprising:
code for identifying use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1]; code for implementing the controlled-Z a gate for a fault-tolerant quantum information processing (QIP) system, wherein the implementation of the controlled-Z a gate includes multiple elements with only six (6) of the elements being controlled-NOT (CNOT) gates; code for mapping the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and code for performing the quantum algorithm based at least in part on the physical representation.

10 . A method for performing a quantum algorithm, comprising:
identifying use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1]; implementing the controlled-Z a gate for a fault-tolerant quantum information processing (QIP) system, wherein the implementation of the controlled-Z a gate includes multiple elements with only four (4) of the elements being T gates, only three (3) of the elements being controlled-NOT (CNOT) gates, and only three (3) of the elements being Hadamard (H) gates; mapping the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and performing the quantum algorithm based at least in part on the physical representation.

11 . The method of claim 10 , wherein the quantum algorithm is a quantum Fourier transform (QFT).

12 . The method of claim 10 , wherein implementing the controlled-Z a gate for the fault-tolerant QIP system includes identifying that the implementation of the controlled-Z a gate is with measurement and feedforward.

13 . The method of claim 10 , wherein the multiple elements of the implementation of the controlled-Z a gate further include:
one (1) parametrized Z a gate, one (1) ancilla, one (1) measurement, and one (1) classically-conditioned controlled Pauli-Z gate.

14 . The method of claim 10 , wherein implementing the controlled-Z a gate includes implementing the controlled-Z a gate without P gates and P † gates.

15 . The method of claim 10 , wherein:
the fault-tolerant QIP system is a trapped-ion QIP system, and mapping the implementation of the controlled-Z a gate includes mapping the implementation of the controlled-Z a gate using multiple trapped-ion-based qubits in the trapped-ion QIP system.

16 . The method of claim 10 , wherein:
the fault-tolerant QIP system is a superconducting QIP system, and mapping the implementation of the controlled-Z a gate includes mapping the implementation of the controlled-Z a gate using multiple superconducting-based qubits in the superconducting QIP system.

17 . A fault-tolerant quantum information processing (QIP) system for performing a quantum algorithm, comprising:
an implementation component configured to:
identify use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1],
implement the controlled-Z a gate for the fault-tolerant QIP system, wherein the implementation of the controlled-Z a gate includes multiple elements with only four (4) of the elements being T gates, only three (3) of the elements being controlled-NOT (CNOT) gates, and only three (3) of the elements being Hadamard (H) gates, and
map the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and
an algorithms component configured to perform the quantum algorithm based at least in part on the physical representation.

18 . A non-transitory computer-readable medium storing code with instructions executable by a processor for performing a quantum algorithm, comprising:
code for identifying use of a controlled-Z a gate as part of the quantum algorithm, wherein a is a parameter and a∈[−1, 1]; code for implementing the controlled-Z a gate for a fault-tolerant quantum information processing (QIP) system, wherein the implementation of the controlled-Z a gate includes multiple elements with only four (4) of the elements being T gates, only three (3) of the elements being controlled-NOT (CNOT) gates, and only three (3) of the elements being Hadamard (H) gates; code for mapping the implementation of the controlled-Z a gate into a physical representation in the fault-tolerant QIP system; and code for performing the quantum algorithm based at least in part on the physical representation.

19 . A method for performing a quantum simulation, comprising:
identifying use of a Heisenberg interaction as part of the quantum simulation; identifying a controlled-Z a gate for implementing the Heise

Assignees

• Ionq Inc

Inventors

• Nam Yunseong
• Maslov Dmitri

Classifications

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• G06F11/004

  Error avoidance (G06F11/07 and subgroups take precedence) · CPC title

• G06F17/5009 Primary

  Physics · mapped topic

• G06N10/00

  Quantum computing, i.e. information processing based on quantum-mechanical phenomena · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title