Method of manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-2019244965-A1
Application number	US-201916386407-A
Country	US
Kind code	A1
Filing date	Apr 17, 2019
Priority date	Nov 22, 2016
Publication date	Aug 8, 2019
Grant date	—

Abstract

A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

First claim

1 .- 30 . (canceled)

31 . A method of manufacturing a semiconductor device, the method comprising:
forming a first active pattern and a second active pattern; on a substrate forming a sacrificial pattern across the first and second active patterns; forming a gate spacer on a sidewall of the sacrificial pattern; removing a first portion of the sacrificial pattern to form an opening; sequentially forming a lower insulation layer and an upper insulation layer that fill the opening; removing second and third portions of the sacrificial pattern to form a first empty space and a second empty space; and removing a side portion of the lower insulation layer exposed through the first and second empty spaces to form a first insulation pattern, wherein the first portion of the sacrificial pattern is between the first and second active patterns, wherein the second portion of the sacrificial pattern crosses the first active pattern, and wherein the third portion of the sacrificial pattern crosses the second active pattern.

32 . The method as claimed in claim 31 , further comprising forming first and second gate electrodes that fill the first and second empty spaces, respectively.

33 . The method as claimed in claim 31 , further comprising forming a device isolation layer to define the first and second active patterns at an upper portion of the substrate, and
wherein the first portion of the sacrificial pattern vertically overlaps the device isolation layer.

34 . The method as claimed in claim 31 , further comprising planarizing the upper insulation layer until exposing a top surface of the sacrificial pattern to form a second insulation pattern in the opening.

35 . The method as claimed in claim 31 , wherein a bottom portion of the lower insulation layer is interposed between the upper insulation layer and the substrate.

36 . The method as claimed in claim 31 , wherein, before forming the upper insulation layer, further comprising anisotropically etching the lower insulation layer, such that the lower insulation layer has a spacer shape.

37 . The method as claimed in claim 31 , further comprising removing an upper portion of the gate spacer exposed through the opening.

38 . A method of manufacturing a semiconductor device, the method comprising:
forming a first active pattern and a second active pattern on a substrate; forming a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern; forming a first insulation pattern between and separating the first and second gate electrodes; forming a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern; and forming a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.

39 . The method as claimed in claim 38 , wherein forming the first and second insulation patterns includes:
sequentially forming a lower insulation layer and the first insulating pattern between the first and second gate electrodes; and removing a side portion of the lower insulation layer to form the second insulation pattern.

40 . The method as claimed in claim 39 , wherein a bottom portion of the lower insulation layer is interposed between the first insulating pattern and the substrate.

41 . The method as claimed in claim 38 , further comprising forming a device isolation layer to define the first and second active patterns at an upper portion of the substrate, and
wherein the first and second insulation patterns vertically overlaps the device isolation layer.

42 . The method as claimed in claim 38 , further comprising removing an upper portion of the gate spacer.

43 . The method as claimed in claim 38 , further comprising forming a gate dielectric pattern between the first active pattern and the first gate electrode and between the first insulation pattern and the first gate electrode.

44 . The method as claimed in claim 38 , further comprising forming a gate capping pattern covering top surfaces of the first and second gate electrodes and a top surface of the first insulation pattern.

45 . A method of manufacturing a semiconductor device, the method comprising:
forming a first active pattern and a second active pattern on a substrate; forming a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern; forming a first insulation pattern between the first and second gate electrodes, the first gate electrode, the first insulation pattern, and the second gate electrode being arranged along a first direction; and forming a second insulation pattern on the first insulation pattern, wherein forming the second insulation pattern includes: forming a lower insulation layer covering a bottom surface and sidewalls of the first insulation pattern; and removing a side portion of the lower insulation layer to expose opposite sidewalls of the first insulation pattern facing the first and second gate electrodes.

46 . The method as claimed in claim 45 , wherein a bottom portion of the lower insulation layer is interposed between the first insulating pattern and the substrate.

47 . The method as claimed in claim 45 , further comprising forming a device isolation layer to define the first and second active patterns at an upper portion of the substrate, and
wherein the first and second insulation patterns vertically overlaps the device isolation layer.

48 . The method as claimed in claim 45 , further comprising forming a gate dielectric pattern between the first active pattern and the first gate electrode and between the first insulation pattern and the first gate electrode.

49 . The method as claimed in claim 45 , further comprising forming a gate capping pattern covering top surfaces of the first and second gate electrodes and a top surface of the first insulation pattern.

50 . The method as claimed in claim 45 , further comprising forming a gate spacer along the first direction on sidewalls of the first gate electrode, of the first insulation pattern, and of the second gate electrode,
wherein the second insulation pattern is between the gate spacer and the first insulation pattern along a second direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Seungsoo
• Lee Jeongyun
• Seong Geumjung
• Jung Hyunho
• Gwak Minchan
• MIN Kyungseok
• Oh Youngmook
• Woo Jae-Hoon
• Lim Bora

Classifications

• H01L27/1116

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L27/1108 Primary

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L27/1104

  Electricity · mapped topic