Esd protection circuit assembly for cmos manufacturing process

Patent metadata

Field	Value
Publication number	US-2019206858-A1
Application number	US-201815986307-A
Country	US
Kind code	A1
Filing date	May 22, 2018
Priority date	Dec 28, 2017
Publication date	Jul 4, 2019
Grant date	—

Abstract

An ESD protection circuit assembly for use in a CMOS manufacturing process is disclosed to include an I/O circuit including a power I/O unit and a signal I/O unit, and an electrostatic discharge clamp circuit connected to the power I/O unit and including a P-type substrate, a series of low voltage P-type structures arranged on the P-type substrate, a plurality of low voltage N-type wells formed on the P-type substrate corresponding to the low voltage P-type structures and a first P-type heavily doped area and a second P-type heavily doped area formed in each low voltage N-type well. By using a series of low voltage P-type structures to provide high ESD tolerance, the ESD protection circuit assembly can be more effectively utilized in the same circuit layout area.

First claim

1 . An ESD protection circuit assembly, comprising:
an I/O circuit comprising a power I/O unit, said power I/O unit comprising a high-voltage power termination pad, a first power line electrically connected to said high-voltage power termination pad, a high-voltage ground termination pad and a second power line electrically connected to said high-voltage ground termination pad; and an electrostatic discharge clamp circuit comprising a P-type substrate, at least three low voltage P-type structures arranged on said P-type substrate and connected in series, a plurality of low voltage N-type wells formed on a top side of said P-type substrate and said at least three low voltage P-type structures each comprises a first P-type heavily doped area and a second P-type heavily doped area formed in each said low voltage N-type well, said first P-type heavily doped area and said second P-type heavily doped area are isolated from each other through a part of said low voltage N-type wells, the said first P-type heavily doped area of the first said low voltage P-type structure being electrically connected to said high-voltage power termination pad through said first power line, the said second P-type heavily doped area of the last said low voltage P-type structure being electrically connected to said high-voltage ground termination pad through said second power line to provide an ESD current discharge path.

2 . The ESD protection circuit assembly as claimed in claim 1 , wherein an emitter, a collector and base of a parasitic PNP bipolar junction transistor are respectively formed on the said first P-type heavily doped area and said second P-type heavily doped area of each said low voltage P-type structure and said low voltage N-type well between the said first P-type heavily doped area and the said second P-type heavily doped area; a parasitic resistance is formed in said low voltage N-type well and electrically connected to the base of said parasitic PNP bipolar junction transistor.

3 . The ESD protection circuit assembly as claimed in claim 1 , wherein said electrostatic discharge clamp circuit further comprises a plurality of low voltage seal rings, said low voltage seal rings being respectively formed in an N-type heavily doped areas of said low voltage N-type wells around the respective said first P-type heavily doped areas and said second P-type heavily doped areas, the said first P-type heavily doped area of the first said low voltage P-type structure and said low voltage seal rings being electrically connected to said high-voltage power termination pad through said first power line.

4 . The ESD protection circuit assembly as claimed in claim 3 , wherein the said second P-type heavily doped area of the preceding said low voltage P-type structure of said electrostatic discharge clamp circuit is electrically connected to said first P-type heavily doped area and said low voltage seal ring which are commonly connected together by the next said low-voltage P-type structure.

5 . The ESD protection circuit assembly as claimed in claim 1 , wherein said electrostatic discharge clamp circuit further comprises a plurality of high voltage seal rings surrounding said low voltage P-type structure, a high voltage P-type doped area formed in said P-type substrate, said second P-type heavily doped are of the last said low voltage P-type structure and said high voltage seal rings being electrically connected to said high-voltage ground termination pad through said second power line.

6 . The ESD protection circuit assembly as claimed in claim 1 , wherein the said second P-type heavily doped area of the preceding said low voltage PMOS structure is electrically connected in series to the said first P-type heavily doped area of the next said low voltage PMOS structure.

7 . The ESD protection circuit assembly as claimed in claim 1 , wherein the number of the series-connected said low voltage P-type structures of said electrostatic discharge clamp circuit is an unconditionally rounded up value obtained by: dividing the N times of the turn-on voltage of one individual said low voltage P-type structure by the predetermined withstand voltage of said electrostatic discharge clamp circuit, in which N is an integer not greater than 3.

8 . An ESD protection circuit assembly, comprising:
an I/O circuit comprising a power I/O unit and a signal I/O unit, said power I/O unit comprising a high-voltage power termination pad, a high-voltage ground termination pad and a second power line electrically connected to said high-voltage ground termination pad, said signal I/O unit comprising a plurality of signal transmission termination pads and a plurality of signal transmission lines respectively electrically connected to said signal transmission termination pads; and an electrostatic discharge clamp circuit comprising a P-type substrate, at least three low voltage P-type structures arranged on the P-type substrate and connected in series, a plurality of low voltage N-type wells formed on a top side of said P-type substrate and said at least three low voltage P-type structures each comprises a first P-type heavily doped area and a second P-type heavily doped area formed in each said low voltage N-type well, said first P-type heavily doped area and said second P-type heavily doped area are isolated from each other through a part of said low voltage N-type wells, said first P-type heavily doped area of the first said low voltage P-type structure being electrically connected to said signal transmission termination pad through said signal transmission line, said second P-type heavily doped area of the last said low voltage P-type structure being electrically connected to said high-voltage ground termination pad through said second power line to provide an ESD current discharge path.

9 . The ESD protection circuit assembly as claimed in claim 8 , wherein an emitter, a collector and base of a parasitic PNP bipolar junction transistor are respectively formed on said first P-type heavily doped area and said second P-type heavily doped area of each said low voltage P-type structure and said low voltage N-type well between said first P-type heavily doped area and said second P-type heavily doped area; a parasitic resistance is formed in said low voltage N-type well and electrically connected to the base of said parasitic PNP bipolar junction transistor.

10 . The ESD protection circuit assembly as claimed in claim 8 , wherein said electrostatic discharge clamp circuit further comprises a plurality of low voltage seal rings, said low type wells around the respective said first P-type heavily doped areas and said second P-type heavily doped areas, said P-type heavily doped area of the first said low voltage P-type structure and said low voltage seal rings being electrically connected to said signal transmission termination pad through said signal transmission line.

11 . The ESD protection circuit assembly as claimed in claim 10 , wherein said second P-type heavily doped area of the preceding said low voltage P-type structure of said electrostatic discharge clamp circuit is electrically connected to said first P-type heavily doped area and said low voltage seal ring which are commonly connected together by the next said low-voltage P-type structure.

12 . The ESD protection circuit assembly as claimed in claim 8 , wherein said electrostatic discharge clamp circuit further comprises a plurality of high voltage seal rings surrounding said low voltage P-type structure, each said high voltage seal ring comprising a high voltage P-type doped area formed in said P-type substrate, the said second P-type heavily doped are of the last said low voltage P-type struc

Assignees

• Egalax_Empia Tech Inc

Inventors

• Lin Po-Chuan
• Shiue Shr-Hau

Classifications

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H01L29/1095

  Electricity · mapped topic

• H01L29/0804

  Electricity · mapped topic