Method of fabricating electrostatic discharge protection structure

Patent metadata

Field	Value
Publication number	US-2016268137-A1
Application number	US-201615159816-A
Country	US
Kind code	A1
Filing date	May 20, 2016
Priority date	Dec 28, 2012
Publication date	Sep 15, 2016
Grant date	—

Abstract

A method of fabricating an electrostatic discharge protection structure includes the following steps. Firstly, a semiconductor substrate is provided. Plural isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate. The well region contains first type conducting carriers. The first conductive region and the second conductive region contain second type conducting carriers. Then, a mask layer is formed on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed. Then, a first implantation process is performed to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

First claim

What is claimed is:

1 . A method of fabricating an electrostatic discharge protection structure, the method comprising steps of:
providing a semiconductor substrate, wherein a plurality of isolation structures, a well region, a first conductive region and a second conductive region are formed in the semiconductor substrate, wherein the well region contains first type conducting carriers, and the first conductive region and the second conductive region contain second type conducting carriers, wherein the well region is arranged between the plurality of isolation structures, and the first conductive region and the second conductive region are formed in a surface of the semiconductor substrate over the well region; forming a mask layer on the surface of the semiconductor substrate, wherein a part of the first conductive region is exposed; and performing a first implantation process to implant the second type conducting carriers into the well region by using the mask layer as an implantation mask, so that a portion of the first type conducting carriers of the well region is electrically neutralized and a first doped region is formed under the exposed part of the first conductive region.

2 . The method according to claim 1 , wherein the first type conducting carriers are holes, and the second type conducting carriers are electrons.

3 . The method according to claim 1 , wherein the first doped region contains the first type conducting carriers, wherein a concentration of the first type conducting carriers of the first doped region is lower than a concentration of the first type conducting carriers of the unneutralized well region.

4 . The method according to claim 1 , wherein the first doped region contains the second type conducting carriers, wherein a concentration of the second type conducting carriers of the first doped region is lower than a concentration of the first type conducting carriers of the unneutralized well region.

5 . The method according to claim 1 , wherein the first doped region is separated from the first conductive region by the unneutralized well region.

6 . The method according to claim 1 , further comprising a step of performing a second implantation process to implant the first type conducting carriers into a part of the unneutralized well region by using the mask layer as an implantation mask, so that a second doped region is formed between the exposed part of the first conductive region and the first doped region.

7 . The method according to claim 6 , wherein a concentration of the first type conducting carriers of the second doped region is higher than a concentration of the first type conducting carriers of the remaining part of the unneutralized well region.

8 . The method according to claim 6 , wherein the second doped region is contacted with a bottom of the first conductive region.

9 . The method according to claim 8 , wherein the first doped region and the second doped region are separated from each other by the remaining part of the unneutralized well region.

Assignees

• United Microelectronics Corp

Inventors

• Wang Chang-Tzu
• Chen Yu-Chun
• Tang Tien-Hao

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10D89/815 Primary

  involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor · CPC title

• H01L27/0277

  Electricity · mapped topic