Electrostatic discharge protection structure

Patent metadata

Field	Value
Publication number	US-9449960-B2
Application number	US-201313937142-A
Country	US
Kind code	B2
Filing date	Jul 8, 2013
Priority date	Jul 8, 2013
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

Provided is an electrostatic discharge (ESD) protection structure including a substrate, a pick-up region, a first MOS device, a second MOS device, a first doped region and a second doped region. The pick-up region is located in the substrate. The first MOS device has a first drain region of a first conductivity type located in the substrate. The second MOS device has a second drain region of the first conductivity type located in the substrate. The first drain region is closer to the pick up region than the second drain region is. The first doped region of a second conductivity type is located under the first doped region. The second doped region of the second conductivity type is located under the second doped region. The area and/or doping concentration of the first doped region is greater than that of the second doped region.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection structure, comprising:
a substrate;
a pick-up region, located in the substrate;
a first MOS device, located on the substrate and comprising a first drain region and a first source region of a first conductivity type;
a second MOS device, located on the substrate and comprising a second drain region and a second source region of the first conductivity type, wherein the first drain region is closer to the pick-up region than the second drain region is;
a first doped region of a second conductivity type, located only under the first drain region; and
a second doped region of the second conductivity type, located only under the second drain region, wherein an area, a doping concentration or both of the first doped region are greater than an area, a doping concentration or both of the second doped region,
wherein there is only one doped region of the second conductivity type under each drain region of the first conductivity type,
wherein the first doped region and the second doped region are disposed in the substrate, and a doping concentration of the first doped region and a doping concentration of the second doped region are different from a doping concentration of the substrate which surrounds the first and second doped regions.

2. The ESD protection structure of claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

3. The ESD protection structure of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

4. The ESD protection structure of claim 1 , wherein the first MOS device and the second MOS device are arranged in parallel to constitute a multi-finger MOS device.

5. The ESD protection structure of claim 1 , wherein the first MOS device and the second MOS device constitute a waffle-type MOS device.

6. The ESD protection structure of claim 1 , wherein the pick-up region has a ring shape, and the first MOS device and the second MOS device are located within a region surrounded by the pick-up region.

7. The ESD protection structure of claim 1 , wherein the substrate is in direct contact with the first doped region and the second doped region, respectively.

8. The ESD protection structure of claim 1 , wherein the substrate surrounds and direct contacts the first drain region and the second drain region.

9. The ESD protection structure of claim 1 , wherein an isolation structure is disposed between the pick-up region and the first source region.

10. An electrostatic discharge (ESD) protection structure, comprising:
a substrate;
a pick-up region, located in the substrate;
a plurality of MOS devices, located on the substrate and respectively having a plurality of drain regions and a plurality of source regions of a first conductivity type;
a plurality of doped regions of a second conductivity type, respectively located only under the drain regions of the MOS devices,
wherein the doped regions are disposed in the substrate, and areas of the doped regions are increased toward the pick-up region, and
wherein there is only one doped region of the second conductivity type under each drain region of the first conductivity type,
wherein a doping concentration of each of the plurality of doped regions is different from a doping concentration of the substrate which surrounds the plurality of doped regions.

11. The ESD protection structure of claim 10 , wherein the first conductivity type is N-type and the second conductivity type is P-type.

12. The ESD protection structure of claim 10 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

13. The ESD protection structure of claim 10 , wherein the MOS devices are arranged in parallel to constitute a multi-finger MOS device.

14. The ESD protection structure of claim 10 , wherein the MOS devices constitute a waffle-type MOS device.

15. The ESD protection structure of claim 10 , wherein the pick-up region has a ring shape, and the MOS devices are located within a region surrounded by the pick-up region.

16. The ESD protection structure of claim 10 , wherein the substrate is in direct contact with the plurality of doped regions.

17. The ESD protection structure of claim 10 , wherein the substrate surrounds and direct contacts the plurality of drain regions.

18. The ESD protection structure of claim 10 , wherein an isolation structure is disposed between the pick-up region and a nearby source region.

Assignees

• United Microelectronics Corp

Inventors

• Wen Yung-Ju
• Wang Chang-Tzu
• Tang Tien-Hao

Classifications

• H10D89/815 Primary

  involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base region of said parasitic bipolar transistor · CPC title

• H01L27/0277 Primary

  Electricity · mapped topic