Integrated circuit having a high cell density

Patent metadata

Field	Value
Publication number	US-10157840-B2
Application number	US-201715468281-A
Country	US
Kind code	B2
Filing date	Mar 24, 2017
Priority date	Dec 2, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.

First claim

What is claimed is:

1. A method comprising:
retrieving cells from a cell library, wherein retrieving the cells includes retrieving first and second cells, each of which includes:
a plurality of gate electrodes, each of the first and second cells being divided by the plurality of the gate electrodes thereof into a plurality of tracks,
a source region,
a contact conductive line that extends from the source region, and
a power conductive line that is coupled to the contact conductive line and that spans across the tracks;

identifying locations for placement of the first and second cells in a layout of an integrated circuit;
placing the first and second cells at the locations in the layout, the first and second cells abutting each other in a vertical direction, such that a first power conductive line of the first cell abuts a second power conductive line of the second cell, the vertical direction being perpendicular to a substrate; and
fabricating the integrated circuit based on the layout.

2. The method of claim 1 , wherein placing the physical cells includes:
defining a line in the layout,
placing the first and second cells such that power vias thereof are on the line, and
abutting the first and second cells against each other.

3. The method of claim 1 , wherein placing the physical cells includes:
abutting the first and second cells against each other,
aligning tracks of the first and second cells with each other, and
checking whether the alignment complies with a design rule.

4. The method of claim 3 , wherein checking whether the alignment complies with the design rule includes determining whether a ratio of power vias connected to the first and second cells to source regions of the first and second cells is equal to or greater than 0.5.

5. The method of claim 3 , wherein checking whether the alignment complies with the design rule includes determining whether to insert a power via at a same track as a source region.

6. The method of claim 3 , wherein checking whether the alignment complies with the design rule includes determining whether to insert a power via at a first track adjacent to a second track of a source region.

7. The method of claim 3 , further comprising re-aligning tracks of the first and second cells based on whether the alignment violates the design rule.

8. The method of claim 1 , further comprising selecting a track at which to insert a power via.

9. The method of claim 8 , further comprising:
connecting a power via to the first cell;
accessing a second cell library to obtain timing information based on a number of power vias of the first cell; and
assigning the obtained timing information to the first cell, whereby the layout is simulated based on the timing information assigned to cells of the layout.

10. A method comprising:
identifying first and second locations for placement of a parent cell and a child cell in a layout of an integrated circuit;
placing, at a first location, a parent cell including a power via configured to receive a supply voltage;
placing, at a second location, a child cell configured to perform a same cell function as the parent cell and including a power via configured to receive the supply voltage, wherein the parent cell and the child cell include different numbers of power vias, the parent and child cells abutting each other in a vertical direction, such that a first power conductive line of the parent cell abuts a second power conductive line of the child cell, the vertical direction being perpendicular to a substrate; and
fabricating the integrated circuit based on the layout.

11. The method of claim 10 , wherein the parent cell and the child cell are of a same cell height.

12. The method of claim 10 , wherein the parent cell and the child cell are of a same cell width.

13. The method of claim 10 , wherein the parent cell and the child cell include a same number of transistors.

14. The method of claim 10 , wherein the parent cell and the child cell are assigned with different timing information.

15. A method comprising:
retrieving cells from a cell library, wherein retrieving the cells includes retrieving first and second cells, each of which includes:
a source region;
a plurality of gate electrodes that divide each of the first and second cells into a plurality of tracks, a first track including the source region;
a power conductive line that is coupled to a contact conductive line and that spans across the plurality of tracks;
a power via that interconnects a supply conductive line and the power conductive line;

identifying locations for placement of the first and second cells in a layout of an integrated circuit;
placing physical cells corresponding to the first and second cells at the locations in the layout, the first and second cells abutting each other in a vertical direction, such that a first power conductive line of the first cell abuts a second power conductive line of the second cell, the vertical direction being perpendicular to a substrate; and
fabricating the integrated circuit based on the layout.

16. The method of claim 15 , wherein:
a second track in the plurality of tracks includes a drain region and a contact via that couples the drain region to a signal conductive line; and
the power via is positionable at a track different from a track at which the contact via resides and from tracks at which contact vias of neighboring cells reside and whereby the power conductive line, and thus the power via, and the contact via have a vertical distance therebetween of less than a threshold of a minimum distance design rule, without violating the minimum distance design rule.

17. The method of claim 15 , wherein each cell is enclosed by a cell boundary that has a top edge at which the power conductive line is disposed.

18. The method of claim 15 , wherein:
the contact conductive line extends from the source region; and
the power conductive line spans across the plurality of tracks.

19. The method of claim 18 , wherein:
each cell further includes a drain region and a contact via that couples the drain region to a signal conductive line; and
the power via and the contact via are at different tracks.

20. The method of claim 19 , wherein the contact via and one of the power conductive line and the power via have a vertical distance therebetween of less than a threshold of a minimum distance design rule.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Sheng-Hsiung
• Wang Chung-Hsing
• Chang Fong-Yuan
• Lu Lee-Chung
• Tien Li-Chun
• Huang Po-Hsiang
• Wang Shao-Huan
• Chen ting yu
• Chen Yen-Pin
• Chen Chun-Chen
• Lin Tzu-Hen
• Cheng tai-yu

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title