Conductive External Connector Structure and Method of Forming

Patent metadata

Field	Value
Publication number	US-2019131263-A1
Application number	US-201816226173-A
Country	US
Kind code	A1
Filing date	Dec 19, 2018
Priority date	Nov 16, 2015
Publication date	May 2, 2019
Grant date	—

Abstract

External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, the method comprising:
immersing a conductive contact into a first plating solution, the first plating solution having a positive first level of agitation; immersing the conductive contact into a second plating solution different from the first plating solution, the second plating solution having a second level of agitation; and immersing the conductive contact into a third plating solution different from the second plating solution, the third plating solution having a third level of agitation greater than either the first level of agitation or the second level of agitation.

2 . The method of claim 1 , wherein the first plating solution plates copper onto the conductive contact.

3 . The method of claim 2 , wherein the second plating solution plates a barrier layer onto the copper.

4 . The method of claim 3 , wherein the third plating solution plates solder onto the barrier layer.

5 . The method of claim 1 , wherein the first level of agitation comprises a first positive level of reciprocation of a first paddle and the third level of agitation comprises a second positive level of reciprocation of the first paddle.

6 . The method of claim 1 , wherein the first level of agitation is relative to a first distance between the conductive contact and a first paddle and the third level of agitation is relative to a second distance between the conductive contact and a second paddle, the second distance being less than the first distance.

7 . The method of claim 1 , wherein the first level of agitation comprises a first magnitude of reciprocation of a first paddle and the third level of agitation comprises a second magnitude of reciprocation of a second paddle.

8 . A method of manufacturing a semiconductor device, the method comprising;
applying a seed layer and a photoresist over a contact over a semiconductor substrate; patterning the photoresist to expose a portion of the seed layer; plating a first conductive layer on the seed layer, wherein after the plating the first conductive layer the first conductive layer has sidewalls in physical contact with the photoresist; and plating solder onto the first conductive layer, wherein during the plating the solder a portion of the photoresist is flexed to expose a portion of, but not all, of the sidewalls of the first conductive layer.

9 . The method of claim 8 , wherein the portion of the sidewalls has a height of about 1 μm to about 15 μm.

10 . The method of claim 9 , wherein the first conductive layer has a height of between about 40 μm to about 70 μm.

11 . The method of claim 8 , wherein the portion of the sidewalls has a height of between about 5% to about 10% of a height of the first conductive layer.

12 . The method of claim 8 , wherein a portion of the solder adjacent to the portion of the sidewalls has a width that is equal to or less than about 1 μm.

13 . The method of claim 8 , wherein the plating the first conductive layer comprises:
plating copper onto the contact; and plating a barrier layer onto the copper.

14 . The method of claim 8 , wherein the photoresist is flexed by placing the first conductive layer into a plating solution with a higher level of agitation than a plating solution used to plate the first conductive layer.

15 . A method of manufacturing a semiconductor device, the method comprising:
placing a conductive contact of a semiconductor wafer into a first plating solution; increasing a first agitation level of the first plating solution to a first constant plating agitation; plating a conductive layer over the conductive contact at the first constant plating agitation; placing the conductive contact of the semiconductor wafer into a second plating solution; increasing a second agitation level of the second plating solution to a second constant plating agitation level, the second constant plating agitation level being higher than the first constant plating agitation, the second constant plating agitation level flexing a photoresist away from the conductive contact; and plating a solder onto the conductive layer at the second constant plating agitation level, the solder comprising silver.

16 . The method of claim 15 , wherein the first agitation level is relative to a first distance between the conductive contact and a first paddle and the second agitation level is relative to a second distance between the conductive contact and a second paddle, the second distance being less than the first distance.

17 . The method of claim 15 , wherein the first agitation level comprises a first positive level of reciprocation of a first paddle and the second agitation level comprises a second positive level of reciprocation of a second paddle.

18 . The method of claim 15 , wherein the first agitation level comprises a first magnitude of reciprocation of a first paddle and the second agitation level comprises a second magnitude of reciprocation of a second paddle.

19 . The method of claim 15 , further comprising reducing a concentration of silver in the solder after the plating the solder onto the conductive layer.

20 . The method of claim 19 , wherein the reducing the concentration of silver comprises at least in part a reflow process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Shih Meng-Fu
• Lo Chun-Yen
• Huang Cheng-Lin
• Chen Wen-Ming
• Huang Chien-Ming
• Liu yuan-fu
• Cheng Yung-Chiuan
• Huang Wei-Chih
• Liu Chen-Hsun
• Chan Chien-Pin
• Hsu Yu-Nu
• Lin Chi-Hung
• Pang Te-Hsun
• Ku Chin-Yu

Classifications

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title