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US-9412654-B1 · Aug 9, 2016 · US
Semiconductor Device
US2019074216A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019074216-A1 |
| Application number | US-201816123214-A |
| Country | US |
| Kind code | A1 |
| Filing date | Sep 6, 2018 |
| Priority date | Sep 7, 2017 |
| Publication date | Mar 7, 2019 |
| Grant date | — |
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- Title
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- Abstract
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- Assignees and inventors
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- First independent claim
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- CPC / IPC classifications
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Abstract
Official abstract text for this publication.
There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor device comprising: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring. 2 . The semiconductor device of claim 1 , wherein a material of the impedance adjustment layer includes a Mott-insulator. 3 . The semiconductor device of claim 1 , wherein a material of the impedance adjustment layer includes vanadium dioxide. 4 . The semiconductor device of claim 1 , further comprising: a barrier layer formed between the impedance adjustment layer and the first wiring or the second wiring, wherein the impedance adjustment layer is in contact with the barrier layer. 5 . The semiconductor device of claim 1 , further comprising: an etching stop layer formed on the dielectric layer, wherein the dielectric layer is formed on the first wiring, the second wiring is formed on the etching stop layer, and the impedance adjustment layer is formed between the dielectric layer and the etching stop layer, and is in contact with the etching stop layer. 6 . The semiconductor device of claim 1 , further comprising: a cap layer formed on the first wiring, wherein the dielectric layer is formed on the cap layer, the second wiring is formed on the dielectric layer, and the impedance adjustment layer is formed between the cap layer and the dielectric layer and is in contact with the cap layer.
Assignees
Inventors
Classifications
Inductive arrangements or effects of, or between, wiring layers · CPC title
Electrical arrangements for controlling or matching impedance · CPC title
Capacitive arrangements or effects of, or between wiring layers · CPC title
comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title
Barrier, adhesion or liner layers · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US2019074216A1 cover?
- There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.
- Who is the assignee on this patent?
- Tokyo Electron Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/074. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Mar 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).