Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices

Patent metadata

Field	Value
Publication number	US-2019067229-A1
Application number	US-201715686484-A
Country	US
Kind code	A1
Filing date	Aug 25, 2017
Priority date	Aug 25, 2017
Publication date	Feb 28, 2019
Grant date	—

Abstract

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

First claim

What is claimed is:

1 . A multi-pin wafer level chip scale package comprising:
one or more solder pillars and one or more solder blocks on a silicon wafer wherein said one or more solder pillars and said one or more solder blocks all have a top surface in a same horizontal plane; a pillar metal layer underlying said one or more solder pillars and electrically connecting said one or more solder pillars with said silicon wafer through an opening in a polymer layer over a passivation layer on said silicon wafer; and a block metal layer underlying said one or more solder blocks and electrically connecting said one or more solder blocks with said silicon wafer through a plurality of via openings through said polymer layer over said passivation layer on said silicon wafer wherein said block metal layer is thicker than said pillar metal layer.

2 . The package according to claim 1 wherein said one or more solder blocks connect to devices having high current of greater than 2 A.

3 . The package according to claim 1 wherein said one or more solder pillars connect to devices having low current less than or equal to 2 A.

4 . The package according to claim 1 wherein said polymer layer comprises a first and a second polymer layer and wherein said pillar metal layer comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at a silicon pad exposed by said opening in said first polymer layer over said passivation layer; and
an under pillar metal (UPM) trace on said RDL trace wherein said second polymer layer is over said RDL trace.

5 . The package according to claim 1 wherein said pillar metal layer comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer.

6 . The package according to claim 1 wherein said pillar metal layer comprises:
an under pillar metal (UPM) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer.

7 . The package according to claim 1 wherein said polymer layer comprises a first and a second polymer layer and wherein said block metal layer comprises:
a redistribution layer via (RDL_VIA) contacting said silicon wafer through said plurality of via openings in said first polymer layer and said passivation layer to said silicon wafer; and
an under block metal (UBM) layer covering said RDL_VIA layer in said plurality of via openings wherein said second polymer layer is over said RDL_VIA layer.

8 . The package according to claim 1 wherein said block metal layer comprises:
an under block metal layer (UBM) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer and having a thickness overlying said plurality of via openings.

9 . The package according to claim 1 wherein said block metal layer and said solder blocks comprise any of a variety of shapes wherein at least one side of said block metal layer or said solder block in a two-dimensional plane is greater than 600 μm.

10 . The package according to claim 1 wherein said top surface of said solder pillars and solder blocks is flat or curved.

11 . The package according to claim 1 wherein:
said pillar metal layer comprises:
a redistribution layer (RDL) trace contacting said silicon wafer at a silicon pad exposed by said opening in said polymer layer over said passivation layer; and
an under pillar metal (UPM) trace on said RDL trace;

said block metal layer comprises:
a redistribution layer via (RDL_VIA) contacting said silicon wafer through said plurality of via openings in said polymer layer and said passivation layer to said silicon wafer; and
an under block metal (UBM) layer covering said RDL_VIA layer in said plurality of via openings; and

said RDL trace has a thickness of at least 4 μm, said UPM trace has a thickness of at least 8 μm, said RDL_VIA layer has a thickness of at least 25 μm, said UBM layer has a thickness of at least 25 μm and a width of at least 600 μm in at least one direction, said solder pillar has a height of at least 120 μm and said solder block has a height of at least 100 μm and a width of at least 600 μm.

12 . A method of fabricating a multi-pin wafer level chip scale package comprising:
providing a silicon wafer having a passivation layer thereon having openings therein to silicon pads on said silicon wafer; coating a first polymer layer on said passivation layer; forming one or more metal traces contacting said silicon pads through openings in said first polymer layer in areas where low current connections are to be made and forming one or more metal blocks over and through vias contacting said silicon pads through openings in said first polymer layer in areas where high current connections are to be made wherein said metal blocks are thicker than said metal traces; forming a solder pillar on each metal trace and forming a solder block on each metal block wherein said solder blocks are wider than said solder pillars and wherein a top surface of each of said solder pillars and solder blocks are in the same horizontal plane to complete said multi-pin wafer level chip scale package.

13 . The method according to claim 12 wherein in said areas where high current connections are to be made said solder blocks can conduct currents of greater than 2 A and wherein in areas where low current connections are to be made said solder pillars can conduct currents equal to or lower than 2 A.

14 . The method according to claim 12 wherein said forming said metal traces, said metal blocks, said solder pillars, and said solder blocks comprises:
patterning said first polymer layer to form first openings to said silicon pads in said low current connection areas and to form vias to said silicon pads in said high current connection areas;
sputtering a redistribution layer (RDL) seed layer over said first polymer layer and in said first openings and vias;
plating a RDL layer on said RDL seed layer in said low current connection areas;
etching said RDL layer in said low current connection areas to form RDL traces;
thereafter sputtering a RDL_VIA seed layer into said vias;
thereafter plating a RDL_VIA layer into and above said vias;
etching said RDL_VIA layer to form RDL_VIAS in said high current connection areas;
thereafter depositing a second polymer layer over said RDL traces and RDL_VIAs and patterning said second polymer layer to provide second openings to said RDL_VIAs and to said RDL traces;
sputtering an under pillar metal (UPM) seed layer on said second polymer layer and within said second openings;
plating a UPM layer on said UPM seed layer in said low current areas wherein said UPM layer and said RDL traces together form said metal traces;
plating solder pillars on and above said metal traces;
thereafter etching away said UPM layer not covered by said solder pillars;
thereafter sputtering an under block metal (UBM) seed layer within said second openings over said RDL_VIAs;
plating a UBM layer on said UBM seed layer in said high current connection areas wherein said RDL_VIA and said UBM layer together form said metal blocks;
plating solder blocks on and above said metal blocks; and
thereafter etching away said UBM layer not covered by said solder blocks.

15 . The method according to claim 12 wherein said forming said metal traces, said metal blocks, said solder pillars, and said solder blocks comprises:
patterning said first polymer layer to form first openings to said silicon pads in sai

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Mohammed Habeeb Mohiuddin
• Aiyandra Rajesh Subraya

Classifications

• H10W74/129

  forming a chip-scale package [CSP] · CPC title

• H10W72/01953

  by etching · CPC title

• H10W72/01938

  in gaseous form, e.g. by CVD or PVD · CPC title

• H10W72/01935

  by plating, e.g. electroless plating or electroplating · CPC title

• H10W72/01235

  by plating, e.g. electroless plating or electroplating · CPC title