Package substrate and semiconductor package including the same
US-2024429153-A1 · Dec 26, 2024 · US
Packaging devices and methods
US9030010B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9030010-B2 |
| Application number | US-201213623502-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 20, 2012 |
| Priority date | Sep 20, 2012 |
| Publication date | May 12, 2015 |
| Grant date | May 12, 2015 |
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Abstract
Official abstract text for this publication.
Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion of each of the plurality of TSVs.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a packaging device, the method comprising: forming a plurality of through-substrate vias (TSVs) in an interposer substrate; recessing the interposer substrate or increasing a thickness of the plurality of TSVs to expose portions of the plurality of TSVs; and coupling a conductive ball to the exposed portion of each of the plurality of TSVs, wherein the exposed portions of each of the plurality of TSVs protrude into a portion of…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9030010B2 cover?
- Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg
- What technology area does this patent fall under?
- Primary CPC classification H10W90/701. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 12 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).