System Related Integrated Circuit, Apparatus and Method

Patent metadata

Field	Value
Publication number	US-2019013813-A1
Application number	US-201816105424-A
Country	US
Kind code	A1
Filing date	Aug 20, 2018
Priority date	Dec 1, 2016
Publication date	Jan 10, 2019
Grant date	—

Abstract

A system includes a processing circuit and a circuit configured to output a given number N of bits of configuration information to be used by the processing circuit. The circuit includes a non-volatile programmable memory configured to output a first group of N bits, N terminals for receiving a second group of N bits, and N logic gates. A first input terminal of each logic gate is connected to a respective bit of output from the non-volatile programmable memory and wherein a second input terminal of each logic gate is connected to a respective terminal of the N terminals.

First claim

What is claimed is:

1 . A system comprising:
a shift register comprising a plurality of bits and configured to receive Q input data bits, wherein Q is a positive integer based on a first signal, and wherein the plurality of bits comprises data bits, address bits, and parity bits; and a multiplexer configured to select an input position of the shift register based on the first signal, wherein the shift register is configured to shift the received Q input data bits from the input position.

2 . The system of claim 1 , further comprising a verification circuit coupled to the shift register, the verification circuit configured to compare the address bits with reference address bits after the shift register shifts-in the Q input data bits.

3 . The system of claim 2 , further comprising a memory block configured to generate the reference address bits.

4 . The system of claim 3 , wherein the memory block comprises a programmable memory, and wherein the reference address bits are based on the programmable memory.

5 . The system of claim 4 , wherein the memory block further comprises a second multiplexer having a first input configured to receive a first portion of a first reference address from the programmable memory, and a second input configured to receive a second reference address, the second multiplexer configured to select between the first portion of the first reference address and the second reference address based on a second signal, and wherein the reference address bits comprises a second portion of the first reference address and bits from an output of the second multiplexer.

6 . The system of claim 4 , wherein the memory block further comprises a plurality of combinational logic gates having a first input configured to receive a first portion of a first reference address from the programmable memory, and a second input configured to receive a second reference address, wherein the reference address bits comprises a second portion of the first reference address and bits from an output of the combinational logic gates.

7 . The system of claim 1 , further comprising an error checking circuit coupled to the shift register, the error checking circuit configured to generate an indicator signal that indicates whether the received Q input data bits have errors based on the data bits and the parity bits.

8 . The system of claim 1 , wherein L empty bits of the shift register are populated with zero, wherein L is an integer number greater or equal to zero, and wherein L is based on the first signal.

9 . The system of claim 1 , wherein the plurality of bits further comprises preamble bits.

10 . The system of claim 9 , further comprising a clock recovery circuit configured to recover a clock based on the preamble bits, and wherein the received Q input data bits are sequentially shifted into the shift register based on the recovered clock.

11 . The system of claim 1 , wherein the system comprises a radio-frequency identification (RFID) application.

12 . The system of claim 1 , further comprising an energy harvesting circuit.

13 . A system comprising:
a register comprising a first shift register and a second shift register, the first and second shift registers comprising a plurality of bits and configured to receive Q input data bits, wherein Q is a positive integer based on a first signal, and wherein the plurality of bits comprises data bits, address bits, and parity bits; a first multiplexer configured to select whether to shift bits of the Q input data bits into the first shift register or the second shift register based on a second signal; and a second multiplexer configured to select an input position of the second shift register based on the first signal, wherein the second shift register is configured to shift bits of the received Q input data bits from the input position based on the first signal.

14 . The system of claim 13 , wherein the first signal is based on bits of the first shift register.

15 . The system of claim 13 , wherein the first shift register comprises preamble bits, a first parity bit of the parity bits and the data bits.

16 . The system of claim 15 , wherein the first shift register further comprises a first address bit of the address bits.

17 . The system of claim 13 , wherein the second signal is indicative of whether the first shift register is loaded completely.

18 . A system comprising:
a shift register comprising 32 bits and configured to receive Q input data bits, wherein Q is equal to either 22 , 25 , 27 , or 32 based on a first signal, and wherein the 32 bits comprises preamble bits, data bits, address bits, and parity bits; and a multiplexer configured to select an input position of the shift register based on the first signal, wherein the shift register is configured to shift the received Q input data bits from the input position.

19 . The system of claim 18 , wherein:
bits 25 to 31 of the shift register correspond to the preamble bits; bit 24 of the shift register corresponds to a first parity bit; bits 20 to 23 of the shift register correspond to the data bits; bit 19 of the shift register corresponds to a second parity bit; bits 15 to 18 of the shift register correspond to a first portion of the address bits; bit 14 corresponds to a third parity bit; and bits 10-13 correspond to a second portion of the address bits.

20 . The system of claim 19 , wherein, when Q is equal to 32,
bit 9 of the shift register corresponds to a fourth parity bit; bits 7-8 of the shift register correspond to a third portion of the address bits; bits 5-6 of the shift register correspond to a fourth portion of the address bits; bit 4 of the shift register corresponds to a fifth parity bit; and bits 0-3 of the shift register corresponds to a fifth portion of the address bits.

Assignees

• St Microelectronics Srl

Inventors

• Pappalardo Francesco
• Notarangelo Giuseppe

Classifications

• G08C2201/91

  Remote control based on location and proximity · CPC title

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03K19/1733

  Controllable logic circuits (H03K19/177 takes precedence) · CPC title

• H03K2217/94021

  with human activation, e.g. processes requiring or being triggered by human intervention, user-input of digital word or analog voltage · CPC title

• H03K19/1737

  using multiplexers (H03K19/1738 takes precedence) · CPC title