Apparatus for charge recovery during low power mode

Patent metadata

Field	Value
Publication number	US-2016294281-A1
Application number	US-201315032981-A
Country	US
Kind code	A1
Filing date	Dec 20, 2013
Priority date	Dec 20, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

Described is an apparatus for power management. The apparatus comprises: a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

First claim

1 . An apparatus comprising:
a first power supply node; a second power supply node; a controllable device coupled to the first power supply node and to the second power supply node, the controllable device operable to short the first power supply node to the second power supply node; a load coupled to the second power supply node; and a charge recovery pump (CRP) coupled to the first and second power supply nodes.

2 . The apparatus of claim 1 , wherein the CRP is operable to turn on when the controllable device is turned off.

3 . The apparatus of claim 1 , wherein the CRP is operable to recover charge from a load capacitance associated to the load and to provide it to the first power supply node.

4 . The apparatus of claim 1 , where in the CRP comprises a voltage doubler.

5 . The apparatus of claim 4 , wherein the CRP comprises a disabling circuit to disable the voltage doubler after a predetermined time.

6 . The apparatus of claim 5 , wherein the disabling circuit comprises a Schmitt Trigger device.

7 . The apparatus of claim 5 , wherein the disabling circuit comprises a Time-to-Delay (TDC) converter.

8 . The apparatus of claim 1 , wherein the CRP comprises a combination of a voltage doubler and a voltage tripler.

9 . The apparatus of claim 6 , wherein the CRP comprises:
a first disabling circuit to disable the voltage doubler and to enable the voltage tripler after a first predetermined time; and a second disabling circuit to disable to the voltage tripler after a second predetermined time.

10 . (canceled)

11 . The apparatus of claim 1 , wherein the CRP is shared with multiple different loads including the load.

12 . The apparatus of claim 11 further comprises logic to recover charge from one or more of the multiple different loads which is in sleep mode, and to provide the recovered charge to another load which is active.

13 . (canceled)

14 . (canceled)

15 . The apparatus of claim 1 , wherein the controllable device is a sleep transistor controllable by a sleep signal.

16 . The apparatus of claim 1 , wherein the CRP includes a capacitor which is shared with a decoupling capacitor.

17 .- 25 . (canceled)

26 . An apparatus comprising:
a power supply node; a plurality of processor cores; a plurality of sleep transistors coupled to the first power supply node, each of the sleep transistors is coupled to a processor core of the plurality of processor cores, wherein each of the processor core has an internal power supply node coupled to the sleep transistor; and a plurality of charge recovery pumps (CRPs), each of which is coupled to a processor core and the power supply node.

27 . The apparatus of claim 26 , wherein each of the CRP is operable to turn on when a sleep transistor coupled to that CRP is turned off.

28 . The apparatus of claim 26 , wherein each of the CRP is operable to recover charge from the internal power supply node and to provide the recovered charge to the power supply node.

29 . The apparatus of claim 26 , wherein each of the CRP comprises a voltage doubler.

30 . The apparatus of claim 29 , wherein each of the CRP comprises a disabling circuit to disable the voltage doubler after a predetermined time.

31 . The apparatus of claim 30 , wherein the disabling circuit comprises a Schmitt Trigger device.

32 . The apparatus of claim 30 , wherein the disabling circuit comprises a Time-to-Delay (TDC) converter.

33 . The apparatus of claim 26 , wherein each of the CRP comprises a combination of a voltage doubler and a voltage tripler.

34 . The apparatus of claim 33 , wherein each of the CRP comprises:
a first disabling circuit to disable the voltage doubler and to enable the voltage tripler after a first predetermined time; and a second disabling circuit to disable to the voltage tripler after a second predetermined time.

35 .- 40 . (canceled)

41 . A system comprising:
a memory unit; a processor coupled to the memory unit, the processor having an apparatus according to any one of apparatus claims 26 to 34 ; and a wireless interface for allowing the processor to communicate with another device.

42 . The system of claim 41 further comprises a display unit.

43 . The system of claim 42 , wherein the display unit is a touch screen.

Assignees

• Intel Corp

Inventors

• Kulkarni Jaydeep P
• Meinerzhagen Pascal A
• Somasekhar Dinesh
• Tschanz James W
• De Vivek K

Classifications

• H03K19/21 Primary

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H03K3/0377

  Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165) · CPC title

• H02J7/00

  Circuit arrangements for charging or discharging batteries or for supplying loads from batteries · CPC title