Package Structures and Methods of Forming

Patent metadata

Field	Value
Publication number	US-2019006317-A1
Application number	US-201816048649-A
Country	US
Kind code	A1
Filing date	Jul 30, 2018
Priority date	Sep 5, 2014
Publication date	Jan 3, 2019
Grant date	—

Abstract

Methods of forming and structures of packages are discussed herein. In an embodiment, a method includes forming a back side redistribution structure, and after forming the back side redistribution structure, adhering a first integrated circuit die to the back side redistribution structure. The method further includes encapsulating the first integrated circuit die on the back side redistribution structure with an encapsulant, forming a front side redistribution structure on the encapsulant, and electrically coupling a second integrated circuit die to the first integrated circuit die. The second integrated circuit die is electrically coupled to the first integrated circuit die through first external electrical connectors mechanically attached to the front side redistribution structure.

First claim

What is claimed is:

1 . A structure comprising:
a first package comprising:
a first integrated circuit die having an active side and a back side opposite from the active side,
an encapsulant laterally encapsulating the first integrated circuit die, a first surface of the encapsulant being coplanar with a surface of a die connector on an active side of the first integrated circuit die, a second surface of the encapsulant being opposite from the first surface of the encapsulant,
a first redistribution structure on the first surface of the of the encapsulant,
a second redistribution structure on the second surface of the encapsulant, and
a through via extending through the encapsulant, a first end of the through via extending into the second redistribution structure, the through via extending over a surface of the second redistribution structure facing the first redistribution structure; and
a second integrated circuit die electrically coupled to the first integrated circuit die through first external electrical connectors, the first external electrical connectors being mechanically attached to the first redistribution structure.

2 . The structure of claim 1 , further comprising second external electrical connectors mechanically attached to the second redistribution structure.

3 . The structure of claim 2 , further comprising an epoxy flux around the second external electrical connectors.

4 . The structure of claim 2 , wherein the second external electrical connectors are mechanically attached to the second redistribution structure through under bump metallurgies.

5 . The structure of claim 1 , further comprising a second package, the second package comprising the second integrated circuit die, the second package being mechanically attached to the first external electrical connectors.

6 . The structure of claim 1 , wherein the first external electrical connectors are directly mechanically attached to the second integrated circuit die.

7 . A structure comprising:
a first redistribution structure comprising:
a first insulating layer; and
metallization layers over the first insulating layer, each of the metallization layers being separated by one or more insulating layers;
through vias on the first redistribution structure, the through vias extending through an uppermost insulating layer of the first redistribution structure, a portion of the through vias extending over an uppermost surface of the uppermost insulating layer; a first integrated circuit die on the first redistribution structure, a front side of the first integrated circuit die comprising a first pad and a first die connector electrically connected to the first pad, a top surface of the through vias being higher than a top surface of the first pad; a second integrated circuit die on the first redistribution structure, a front side of the second integrated circuit die comprising a second pad and a second die connector electrically connected to the second pad, the top surface of the through vias being higher than a top surface of the second pad; encapsulant around the first integrated circuit die and second integrated circuit die, wherein a top surface of the through vias, a top surface of the encapsulant, and the top surface of the first die connector are co-planar; a second redistribution structure on the encapsulant, an active side of the first integrated circuit die facing the second redistribution structure, an active side of the second integrated circuit die facing the second redistribution structure; and a packaged integrated circuit die coupled to the second redistribution structure by first external electrical connectors mechanically attached to the second redistribution structure, an active side of the packaged integrated circuit die facing away from the second redistribution structure, wherein the packaged integrated circuit die extends completely over the first integrated circuit die and the second integrated circuit die.

8 . The structure of claim 7 , further comprising second external electrical connectors on the first redistribution structure, wherein the first redistribution structure is interposed between the second external electrical connectors and the through vias.

9 . The structure of claim 8 , wherein the second external electrical connectors comprise solder extending through the first insulating layer to a first metallization layer of the metallization layers.

10 . The structure of claim 9 , further comprising a backside film adjacent the first insulating layer, wherein the solder extends through the backside film.

11 . The structure of claim 8 , wherein the second external electrical connectors comprise an under bump metallization and solder, wherein the under bump metallization extends through the first insulating layer to a first metallization layer of the metallization layers, wherein the under bump metallization is interposed between the solder and the first metallization layer.

12 . The structure of claim 11 , further comprising a flux completely covering a sidewall of the under bump metallization.

13 . The structure of claim 11 , further comprising a backside film adjacent the first insulating layer, wherein the under bump metallization extends through the backside film.

14 . A structure comprising:
a first redistribution structure comprising:
a first insulating layer;
a first metallization layer;
a second metallization layer, wherein the first metallization layer is interposed between the second metallization layer and the first insulating layer; and
a second insulating layer, wherein the second metallization layer is interposed between the second insulating layer and the first metallization layer;
a through via on the first redistribution structure, a portion of the through via extending through the second insulating layer to the second metallization layer; a first integrated circuit die on the first redistribution structure; encapsulant around the first integrated circuit die and the through via, wherein a top surface of the through via, a top surface of the encapsulant, and the top surface of the first integrated circuit die are co-planar; a second redistribution structure on the encapsulant, an active side of the first integrated circuit die facing the second redistribution structure; a packaged integrated circuit die coupled to the second redistribution structure by a first external electrical connector, wherein the packaged integrated circuit die extends completely over the first integrated circuit die; and a second external electrical connector extending through the first insulating layer.

15 . The structure of claim 14 , further comprising a second integrated circuit die, wherein the encapsulant encapsulates the second integrated circuit die.

16 . The structure of claim 15 , wherein the packaged integrated circuit die extends completely over the second integrated circuit die.

17 . The structure of claim 14 , further comprising a third insulating layer directly contacting the first insulating layer, wherein the second external electrical connector extends through the third insulating layer.

18 . The structure of claim 14 , wherein the second external electrical connector comprises solder directly contacting the first metallization layer.

19 . The structure of claim 14 , wherein a portion of the through via extends along a surface of the second insulating layer facing the second redistribution structure.

20 . The structure of claim 14 , wherein a surface

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Chen-Hua
• Yeh Der-Chyang
• Chen Hsien-Wei

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title