Methods of forming multi-chip package structures

Patent metadata

Field	Value
Publication number	US-2019006291-A1
Application number	US-201715635555-A
Country	US
Kind code	A1
Filing date	Jun 28, 2017
Priority date	Jun 28, 2017
Publication date	Jan 3, 2019
Grant date	—

Abstract

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a first die disposed on a substrate, a second die disposed on the substrate, a molding compound disposed between the first die and the second die, wherein the molding compound is disposed on a top surface of the substrate. An epoxy material is disposed between a top portion of a sidewall of the first die and the molding compound, and a thermal interface material (TIM) is disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

First claim

1 . A microelectronic package structure comprising:
a first die on a substrate; a second die on the substrate adjacent the first die; an array of interconnect structures between a bottom surface of the first die and a top surface of the substrate; a first portion of an epoxy material on a top portion of a sidewall of the first die; a second portion of the epoxy material surrounding the array of interconnect structures; a molding compound, wherein a first portion of the molding compound is adjacent the first portion and the second portion of the epoxy material, wherein the first portion of the molding compound is on the top surface of the substrate and is adjacent a first sidewall of the second die, and wherein the first portion of the epoxy material is between the first portion of the molding compound and the top portion of the sidewall of the fir at die, wherein a top surface of the first portion of the molding compound, a top surface of the first portion of the epoxy material, and a top surface of the first die share a common plane with each other; a third portion of the epoxy material on a second sidewall of the second die, wherein the third portion of the epoxy material comprises a sidewall that is parallel with the second sidewall of the second die; and a second portion of the molding compound adjacent the third portion of the epoxy material, wherein a sidewall of the second portion of the molding compound is parallel with the second sidewall of the second die.

2 . The microelectronic package structure of claim 1 wherein a thermal interface material (TIM) is on a top surface of the first die, on a top surface of the second die, on a top surface of the first epoxy portion, and on a top surface of the third epoxy portion.

3 . The microelectronic package structure of claim 1 wherein a cooling solution is on a top surface of the TIM.

4 . The microelectronic package structure of claim 1 wherein the molding compound comprises an epoxy molding compound.

5 . The microelectronic package structure of claim 1 wherein the first portion, the second portion, and the third portion of the epoxy material comprise an underfill material.

6 . The microelectronic package structure of claim 1 wherein a top surface of the molding compound, a top surface of the first portion of the epoxy material, a top surface of the third portion of the epoxy material, a top surface of the first die, and a top surface of the second die share a common plane with each other.

7 . The microelectronic package structure of claim 2 wherein a width of the top surface of the third portion of the epoxy material and a width of the top surface of the first portion of the epoxy material are substantially equal.

8 . The microelectronic package structure of claim 1 wherein an additional plurality of interconnect structures is beneath the second die, and is surrounded by the epoxy material.

9 . A microelectronic package structure comprising:
a first die on a substrate; a second die on the substrate; a molding compound between the first die and the second die, adjacent a first sidewall of the second die, wherein the molding compound is on a top surface of the substrate; a first portion of an epoxy material between a top portion of a sidewall of the first die and the molding compound; a second portion of the epoxy material on a second sidewall of the second die, wherein the second portion of the epoxy material comprises a sidewall that is parallel with the second sidewall of the second die; and a thermal interface material (TIM) disposed on top surfaces of the first and second die, wherein the TIM extends over the entire length of the substrate.

10 . The microelectronic package structure of claim 9 wherein an additional portion of the molding compound is adjacent the second portion of the epoxy material, wherein a sidewall of the additional portion of the molding compound is parallel with the second sidewall of the second die.

11 . The microelectronic package structure of claim 9 wherein the TIM is disposed on a top surface of the first die, on a top surface of the second die, on a top surface of the first epoxy portion, and on a top surface of the second epoxy portion.

12 . The microelectronic package structure of claim 9 wherein the top surfaces of the first die and the second die are coplanar with each other.

13 . The microelectronic package structure of claim 9 wherein the TIM is on a top surface of the molding compound.

14 . The microelectronic package structure of claim 9 wherein the first portion of the epoxy material extends between a top portion of the first sidewall of the second die and the molding compound.

15 . The microelectronic package structure of claim 9 wherein a top surfaces of the first and second portions of the molding compound, a top surface of the first die, and a top surface of the second die share a common plane.

16 . The microelectronic package structure of claim 9 , wherein a cooling solution is on a top surface of the TIM.

17 . A method of forming a microelectronic package comprising:
forming a molding compound on a first portion of a substrate, wherein a second portion of the substrate remains free of the molding compound; attaching a die on the portion of the substrate that is free of the molding compound, wherein a first gap is located between a first sidewall of the die and the molding compound, and wherein a second gap is located between a second sidewall of the die and the molding compound; forming an underfill material in the first gap and forming the underfill material in the second gap.

18 . The method of claim 17 wherein forming the underfill material comprises filling the first gap and filling the second gap with the underfill material by capillary action.

19 . The method of claim 17 wherein the die comprises a plurality of interconnect structures disposed between the die and the substrate, and wherein forming the epoxy material comprises forming the underfill material around the plurality of interconnect structures.

20 . The method of claim 19 further comprising attaching a second die adjacent the first die, wherein the molding compound is adjacent a first sidewall of the second die.

21 . The method of claim 20 further comprising wherein the molding compound is adjacent a second sidewall of the second die, and the underfill material is disposed in a gap between the first sidewall of the second die and the molding compound.

22 . The method of claim 21 further comprising planarizing the top surfaces of the first die and the second die, planarizing top surfaces of the molding compound, and planarizing top surfaces of the underfill material, wherein the top surfaces of the first and second die share a common plane, by using a grinding process.

23 . The method of claim 22 further comprising forming a thermal interface material (TIM) on the backside of the first die and on a backside of the second die, wherein the TIM extends over the entire length of the substrate.

24 . The method of claim 23 further comprising attaching a cooling solution on a top surface of the TIM.

25 . The method of claim 17 wherein forming the molding compound on a substrate further comprises forming the molding compound on a panel of substrates.

Assignees

• Intel Corp

Inventors

• Neal Nicholas
• Haehn Nicholas S

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title