Control circuit for controlling reset operation

Patent metadata

Field	Value
Publication number	US-2018367136-A1
Application number	US-201815878363-A
Country	US
Kind code	A1
Filing date	Jan 23, 2018
Priority date	Jun 16, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

A control circuit includes a reset circuit and a determination circuit. The reset circuit is coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation. The determination circuit is coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

First claim

What is claimed is:

1 . A control circuit, comprising:
a reset circuit coupled to a digital frequency divider of a phase locked loop circuit and configured to perform a reset operation; and a determination circuit coupled to the reset circuit and configured to determine whether a first predetermined time interval has elapsed so as to control the reset circuit to stop performing the reset operation when the first predetermined time interval has elapsed.

2 . The control circuit of claim 1 , wherein performing the reset operation comprises:
transmitting at least one reset signals each having a pulse waveform to the digital frequency divider continually; keeping a reset signal being transmitted to the digital frequency divider to be at an enabling level; or transmitting at least one reset signal to the digital frequency divider after an analog frequency divider of the phase locked loop circuit has stabilized and before the first predetermined time interval has elapsed.

3 . The control circuit of claim 2 , wherein stopping performing the reset operation comprises stopping transmitting the reset signal to the digital frequency divider.

4 . The control circuit of claim 1 , wherein the phase locked loop circuit further comprises an analog frequency divider coupled to the digital frequency divider, and the first predetermined time interval corresponds to a time required for the analog frequency divider to stabilize.

5 . The control circuit of claim 4 , wherein the determination circuit determines whether the first predetermined time interval has elapsed by counting.

6 . The control circuit of claim 5 , wherein:
the phase locked loop circuit further comprises an oscillation source; the control circuit further comprises:
an operation voltage generation circuit, comprising:
an output terminal coupled to the analog frequency divider; and

a first capacitor, comprising:
a first terminal coupled to the output terminal of the operation voltage generation circuit; and
a second terminal coupled to the oscillation source;

the reset circuit comprises:
an output terminal configured to perform the reset operation or stop the reset operation; and
the first predetermined time interval corresponds to the time required for a voltage of the first terminal of the first capacitor to reach a ratio of a predetermined voltage.

7 . The control circuit of claim 6 , wherein the operation voltage generation circuit further comprises:
a bias voltage generator, comprising:
an output terminal configured to provide a bias voltage, wherein the bias voltage is a stable value substantially; and
a first resistor, comprising:
a first terminal coupled to the output terminal of the operation voltage generation circuit; and
a second terminal coupled to the output terminal of the bias voltage generator and configured to receive the bias voltage.

8 . The control circuit of claim 6 , wherein:
the determination circuit comprises a flip flop comprising:
a clock terminal coupled to a clock source and configured to receive a clock signal;
an input terminal configured to receive second data; and
an output terminal configured to output first data according to the second data and the clock signal; and
the reset circuit further comprises a logic circuit configured to offset the first data by a fixed value so as to update the second data, the logic circuit comprising:
an input terminal coupled to the output terminal of the flip flop and configured to receive the first data;
a first output terminal coupled to the input terminal of the flip flop and configured to output the second data; and
a second output terminal coupled to the output terminal of the reset circuit and configured to perform the reset operation when the first data has not yet reached a constant or configured to stop performing the reset operation when the first data has reached the constant, the constant corresponding to the first predetermined time interval.

9 . The control circuit of claim 4 , wherein the determination circuit is further coupled to the analog frequency divider, and the determination circuit determines whether the first predetermined time interval has elapsed according to a tested voltage at the analog frequency divider.

10 . The control circuit of claim 9 , wherein:
the phase locked loop circuit further comprises an oscillation source; the control circuit further comprises:
an operation voltage generation circuit, comprising:
an output terminal coupled to an input terminal of the analog frequency divider; and

a first capacitor, comprising:
a first terminal coupled to the output terminal of the operation voltage generation circuit; and
a second terminal coupled to the oscillation source;

the reset circuit comprises:
an output terminal configured to perform the reset operation or stop performing the reset operation;
the first predetermined time interval corresponds to the time required for a voltage of the first terminal of the first capacitor to reach a ratio of a predetermined voltage; the analog frequency divider is configured to receive the tested voltage; and the voltage of the first terminal of the first capacitor corresponds to the tested voltage.

11 . The control circuit of claim 10 , wherein:
the operation voltage generation circuit further comprises:
a bias voltage generator, comprising:
an output terminal configured to provide a bias voltage, wherein the bias voltage is a stable value substantially; and

a first resistor, comprising:
a first terminal coupled to the output terminal of the operation voltage generation circuit; and
a second terminal coupled to the output terminal of the bias voltage generator and configured to receive the bias voltage;

the determination circuit comprises a detection circuit comprising:
a first terminal coupled to the second terminal of the first resistor and configured to receive the bias voltage;
a second terminal; and
a third terminal coupled to a first reference voltage terminal;
the reset circuit further comprises:
a comparator comprising:
a first terminal coupled to the output terminal of the bias voltage generator and configured to receive the bias voltage;
a second terminal coupled to the second terminal of the detection circuit and configured to receive a third operation voltage corresponding to the tested voltage; and
an output terminal coupled to the output terminal of the reset circuit and configured to stop the reset operation when the third operation voltage reaches the bias voltage substantially; and

the first predetermined time interval corresponds to the time required for the third operation voltage to reach the bias voltage substantially.

12 . The control circuit of claim 11 , wherein:
the determination circuit further comprises:
an offset circuit coupled between the second terminal of the detection circuit and the second terminal of the comparator and configured to provide an offset voltage so as to adjust a voltage level at the second terminal of the detection circuit; and
the third operation voltage equals a sum of a voltage at the second terminal of the detection circuit and the offset voltage.

13 . The control circuit of claim 12 , wherein the offset circuit comprises a transistor comprising:
a first terminal coupled to the second terminal of the comparator; a second terminal coupled to a second reference voltage terminal; and a control terminal coupled the second terminal of the detection circuit.

14 . The control circuit of claim 11 , wherein the detection circuit comprises:
a second resistor, comprising

Assignees

• Richwave Technology Corp

Inventors

• Wu Juang-Shiung

Classifications

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03K17/22 Primary

  Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) · CPC title

• H03L7/0807 Primary

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03L7/08

  Details of the phase-locked loop · CPC title