Apparatus and methods for phase-locked loop oscillator calibration and lock detection

Patent metadata

Field	Value
Publication number	US-9240795-B2
Application number	US-201414169813-A
Country	US
Kind code	B2
Filing date	Jan 31, 2014
Priority date	Jan 31, 2014
Publication date	Jan 19, 2016
Grant date	Jan 19, 2016

Abstract

A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.

First claim

What is claimed is:

1. A method of calibrating a phase-locked loop (PLL) having at least a frequency divider, the method comprising:
generating a lock window signal based on a feedback signal generated by the frequency divider, the lock window signal forming an active lock window relative to each significant edge of the feedback signal;
generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal; and
estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.

2. The method of claim 1 , wherein a given calibration measurement is immediately aborted if the number of consecutive samples of the sampled window signal that are active is less than a predefined lower limit corresponding to excessive phase or frequency offset.

3. The method of claim 1 , wherein each significant edge is one of a rising edge and a falling edge.

4. The method of claim 1 , wherein each active lock window extends a predefined fraction of a period of the feedback signal and is approximately centered about the significant edge of the feedback signal.

5. The method of claim 1 , wherein further calibration measurements are immediately aborted if the number of consecutive samples of the sampled window signal that are active is greater than a predefined upper limit corresponding to phase-lock.

6. The method of claim 1 , wherein further calibration measurements are immediately aborted if an associated calibration space has been exhausted and if the number of consecutive samples of the sampled window signal that are active is less than a predefined lower limit corresponding to excessive phase or frequency offset.

7. The method of claim 1 , further comprising generating a leading edge indicator based on a comparison between the significant edge of the reference signal and the significant edge of the feedback signal, and adjusting an output frequency of a local oscillator based on a state of the leading edge indicator.

8. The method of claim 7 , wherein the output frequency of the local oscillator is increased if the state of the leading edge indicator indicates the reference signal to be leading relative to the feedback signal, and decreased if the state of the leading edge indicator indicates the reference signal to be lagging relative to the feedback signal.

9. A method of calibrating a phase-locked loop (PLL) having at least a frequency divider and a local oscillator, the method comprising:
sampling of a lock window signal at each significant edge of a reference signal, the lock window signal forming an active lock window approximately centered about each significant edge of a feedback signal generated by the frequency divider;
determining a number of consecutive samples of the lock window signal that are active;
updating the local oscillator based on a state of the feedback signal if the number of consecutive active samples is less than a predefined lower limit corresponding to excessive phase offset; and
aborting calibration measurements if the number of consecutive active samples is greater than a predefined upper limit corresponding to phase-lock.

10. The method of claim 9 , further comprising generating a leading edge indicator based on a comparison between the significant edge of the reference signal and the significant edge of the feedback signal, and adjusting an output frequency of the local oscillator based on a state of the leading edge indicator.

11. The method of claim 10 , wherein the local oscillator is updated based on the state of the feedback signal as indicated by the leading edge indicator.

12. The method of claim 9 , wherein the local oscillator is updated if an associated calibration space has not been exhausted, and wherein further calibration measurements are immediately aborted with a corresponding error indication if the calibration space has been exhausted.

13. The method of claim 9 , wherein each active lock window extends a predefined fraction of a period of the feedback signal and is approximately centered about the significant edge of the feedback signal.

14. A phase-locked loop (PLL), comprising:
a local oscillator configured to generate an output signal;
a feedback divider configured to generate a feedback signal and a lock window signal in response to the output signal;
a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and generate a sampled window signal based on samples of the lock window signal with the reference signal; and
a calibration controller configured to determine a number of consecutive samples in the sampled window signal that are active, and estimate a phase offset based on the number of consecutive active samples.

15. The PLL of claim 14 , wherein the calibration controller is further configured to update the local oscillator according to a state of the feedback signal relative to the reference signal if the number of consecutive active samples is less than a predefined lower limit corresponding to excessive phase offset, and aborting calibration measurements if the number of consecutive active samples is greater than a predefined upper limit corresponding to phase-lock.

16. The PLL of claim 14 , wherein the calibration controller is further configured to determine whether an associated calibration space has been exhausted, the calibration controller being configured to update the local oscillator if the calibration space has not been exhausted, and abort further calibration measurements with a corresponding error indication if the calibration space has been exhausted.

17. The PLL of claim 14 , wherein the phase detector is further configured to generate a leading edge indicator based on a comparison between the reference signal and the feedback signal, and the calibration controller is further configured to adjust an output frequency of the local oscillator based on a state of the leading edge indicator.

18. The PLL of claim 17 , wherein the output frequency of the local oscillator is increased if the state of the leading edge indicator indicates the reference signal to be leading relative to the feedback signal, and decreased if the state of the leading edge indicator indicates the reference signal to be lagging relative to the feedback signal.

19. The PLL of claim 17 , wherein the calibration controller further comprises a frequency controller configured to adjust the output frequency of the local oscillator in response to the sampled window signal and the leading edge indicator.

20. The PLL of claim 14 , wherein the phase detector and the frequency divider are concurrently released in approximate synchronization with a significant edge of the reference signal.

Assignees

• Silicon Lab Inc

Inventors

• Reichelt Pål Øyvind
• Janbu Øyvind

Classifications

• H03K5/135

  by the use of time reference signals, e.g. clock signals · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title

• H03L7/095 Primary

  using a lock detector (H03L7/087 takes precedence) · CPC title

• H03L7/199

  with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation · CPC title

• H03L7/104

  using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence) · CPC title