High availability and energy-efficient watchdog timer

Patent metadata

Field	Value
Publication number	US-2017010933-A1
Application number	US-201514794778-A
Country	US
Kind code	A1
Filing date	Jul 8, 2015
Priority date	Jul 8, 2015
Publication date	Jan 12, 2017
Grant date	—

Abstract

Examples for an intelligent watchdog timer for a computing device are described herein. The watchdog timer operates a watchdog counter that repetitively counts a watchdog count interval from an initial value to a final value. The watchdog counter is continually reset if the device is functioning properly. If the watchdog timer is allowed to reach a final count value, a processor reset is initiated. Several components operate to detect the current mode of operation of the processor or an operating system, and predict, in part based on user context, when different power states may occur. The components also forecast when the watchdog timer is scheduled to reach the final count value. Based on the forecasts of when the watchdog timer will reach the final count value and the predictions of future power states of the processor or operating system, the watchdog counter is selectively disabled or reset.

First claim

What is claimed is:

1 . An apparatus, comprising:
a watchdog timer configured to count a watchdog count interval from an initial time to an expiration time; a memory area configured to store data that indicates the initial time and the expiration time; and a processor programmed to:
execute an operating system,
detect a current mode of operation for the operating system to operate in a high power-consuming state during a first timeframe and a low power-consuming state during a second timeframe,
determine that the expiration time of the watchdog timer is set to occur during the second timeframe when the operating system will operate in the low power-consuming state, and
disable the watchdog timer based upon the expiration time being set to occur when the operating system will operate in the low power-consuming state.

2 . The apparatus of claim 1 , wherein the watchdog timer comprises a hardware counter.

3 . The apparatus of claim 2 , wherein a watchdog component of the operating system is configured to disable the watchdog timer by disabling the hardware counter.

4 . The apparatus of claim 1 , wherein the processor is further programmed to:
analyze previous bark interrupts; and disable the watchdog timer at a second expiration time based on the previous bark interrupts.

5 . The apparatus of claim 1 , wherein a watchdog component of the operating system is configured to disable the watchdog timer before the second timeframe begins.

6 . The apparatus of claim 1 , wherein the operating system is set to operate in the low power-consuming state comprises an operating system operating in an idle or off state.

7 . The apparatus of claim 1 , wherein the watchdog timer, the memory area, and the processor are housed in at least one member of a group comprising a smart phone, a tablet, a computer, a gaming console, and a server.

8 . The apparatus of claim 1 , wherein the processor is configured to:
determine that the current mode of operation dictates the operating system is set to additionally operate in the high power-consuming state during a third timeframe, determine a second expiration time of the watchdog timer being set to occur in the third timeframe when the operating system will operate in the high power-consuming state, and reset the watchdog timer at the second expiration time during the third timeframe.

9 . The apparatus of claim 1 , wherein the processor comprises at least one member of a group comprising a field-programmable gate array, an application-specific integrated circuit, a system-on-a-chip system, and a complex programmable logic device.

10 . A method for operating a watchdog timer for a computing device, the watchdog timer counting a watchdog count interval from an initial time to an expiration time, the method comprising:
detecting a current mode of operation of the computing device that requires a processor to function in a high power-consuming state and a low power-consuming state; determining the expiration time of the watchdog timer is set to occur while the processor is scheduled to function in the low power-consuming state; and disabling the watchdog timer when the expiration time is forecast to occur while the processor is scheduled to function in the low power-consuming state.

11 . The method of claim 10 , wherein the watchdog timer comprises a hardware counter.

12 . The method of claim 11 , further comprising:
analyzing previous bark interrupts; and disabling the watchdog timer at a second expiration time based on the previous bark interrupts.

13 . The method of claim 10 , wherein said disabling of the watchdog timer occurs before the processor functions in the low power-consuming state.

14 . The method of claim 10 , wherein the watchdog counter comprises one or more hardware counters.

15 . The method of claim 10 , further comprising:
determining a second expiration time of the watchdog timer is set to occur while the processor is scheduled to function in the high power-consuming state; and resetting the watchdog timer when the expiration time is forecast to occur while the processor is scheduled to function in the low power-consuming state.

16 . The method of claim 10 , wherein the current mode of operation comprises at least one member of a group comprising an audio playback mode, a video playback mode, a video record mode, a video-conference mode, a connected standby mode, a camera mode, a web browser mode, and a typing mode.

17 . The method of claim 10 , wherein the computing device comprises at least one member of a group comprising a smart phone, a tablet, a computer, a gaming console, and a server.

18 . One or more computer-storage media embodying computer-executable components on a computing device, having at least one processor, for managing a watchdog timer configured to count a watchdog count interval from an initial value to a final value, said components comprising:
a mode detection component that when executed causes the at least one processor to detect a current mode of operation of the computing device; a scheduling component that when executed causes the at least one processor to determine when the mode of operation dictates the at least one processor will function in different power states and when the watchdog timer will finish counting the watchdog count interval; and a watchdog component that when executed causes the at least one processor to selectively disable or reset the watchdog timer based on which of the power states in which the at least one processor is scheduled to function at the time the watchdog timer will finish counting the watchdog count interval.

19 . The computer-storage media of claim 18 , wherein the watchdog component is configured to:
reset the watchdog timer to an initial count value when the watchdog count interval is determined to expire while the at least one processor is scheduled to function in a higher state of power consumption, and disable the watchdog timer to the when the watchdog count interval is determined to expire while the at least one processor is scheduled to function in a lower state of power consumption.

20 . The computer-storage media of claim 18 , wherein the watchdog counter comprises a hardware counter.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Wang Bin
• Zhu Robert Yu
• Wu Qipeng
• Zhang Dejun
• Zhao Pengxiang
• Chin Ying N

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• G06F11/0736

  in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function (testing or monitoring of automated control systems G05B23/02) · CPC title

• G06F11/0757 Primary

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F1/24

  Resetting means · CPC title