Method and apparatus for reducing capacitance of input/output pins of memory device

Patent metadata

Field	Value
Publication number	US-2018366453-A1
Application number	US-201715625350-A
Country	US
Kind code	A1
Filing date	Jun 16, 2017
Priority date	Jun 16, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

In one embodiment, an apparatus comprises a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material.

First claim

1 . An apparatus comprising:
a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; a lower metal layer below the tier; a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier; and a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material; wherein the first channel has a plurality of different widths at different layers of the tier between a top and a bottom of the first channel.

2 . The apparatus of claim 1 , further comprising a second channel through a second portion of the tier, the second channel surrounding the via, the second channel comprising the second dielectric material.

3 . The apparatus of claim 2 , wherein the second channel surrounds the first channel.

4 . The apparatus of claim 1 , wherein the first channel is formed by applying a plurality of masks and etching to different depths of the tier with each applied mask, wherein the masks are also used to form channels for vias that each couple to a respective first layer of the tier.

5 . The apparatus of claim 1 , wherein the width of the first channel increases monotonically from the bottom of the first channel to the top of the first channel.

6 . The apparatus of claim 1 , wherein the width of the first channel at the bottom of the channel is between 3 and 5 microns.

7 . The apparatus of claim 1 , wherein the width of the first channel at any depth of the first channel is between 150 and 300 nanometers.

8 . The apparatus of claim 1 , wherein the first dielectric material and the second dielectric material both comprise silicon dioxide.

9 . The apparatus of claim 1 , wherein the second dielectric material comprises silicon dioxide.

10 . The apparatus of claim 1 , wherein at least a portion of a first layer of the tier forms at least a portion of a wordline of a NAND memory array.

11 . A method comprising:
forming a lower metal layer above a substrate; forming a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material; and forming a first channel through a portion of the tier, the first channel to surround a via that is to couple the lower metal layer to a bond pad, the first channel comprising a second dielectric material; wherein the first channel has a plurality of different widths at different layers of the tier between a top and a bottom of the first channel.

12 . The method of claim 11 , further comprising forming a second channel through a portion of the tier, the second channel to surround the via, the second channel comprising the second dielectric material.

13 . The method of claim 12 , wherein the second channel surrounds the first channel.

14 . The method of claim 11 , wherein the first channel is formed by applying a plurality of masks and etching to different depths of the tier with each applied mask, wherein the masks are also used to form channels for vias that each couple to a respective first layer of the tier.

15 . The method of claim 11 , wherein the first channel is formed by applying a mask is also used to form channels isolating memory array blocks from each other.

16 . A system comprising:
a semiconductor package comprising:
a first input/output pin; and
a first memory chip, the first memory chip comprising:
a tier comprising alternating first and second layers, wherein the first layers comprise a first conductive material and the second layers comprise a first dielectric material;
a lower metal layer below the tier;
a bond pad above the tier, the bond pad coupled to the lower metal layer by a via extending through the tier, the bond pad further coupled to the first input/output pin; and
a first channel formed through a portion of the tier, the first channel surrounding the via, the first channel comprising a second dielectric material, wherein the first channel has a plurality of different widths at different layers of the tier between a top and a bottom of the first channel; and
a second channel formed through a second portion of the tier, the second channel surrounding the via, the second channel comprising the second dielectric material, wherein the second channel surrounds the first channel, wherein the second channel is separated from the first channel by a third portion of the tier comprising the alternating first and second layers.

17 . The system of claim 16 , further comprising a processor coupled to the first input/output pin.

18 . The system of claim 17 , further comprising one or more of: a battery communicatively coupled to the processor, a display communicatively coupled to the processor, or a network interface communicatively coupled to the processor.

19 . The system of claim 16 , further comprising a plurality of NAND memory cells formed within the tier.

20 . The system of claim 16 , wherein the first memory chip further comprises a plurality of additional channels formed through portions of the tier, the plurality of additional channels each surrounding the via, the plurality of additional channels each comprising the second dielectric material.

21 . The apparatus of claim 1 , further comprising a third channel formed through a fourth portion of the tier, the third channel surrounding the via, the third channel comprising the second dielectric material, wherein the third channel surrounds the first channel and second channel, wherein the third channel is separated from the second channel by a fifth portion of the tier comprising the alternating first and second layers.

Assignees

• Intel Corp

Inventors

• Carlson Merri Lyn
• Zhu Hongbin
• Haller Gordon A
• Davis James E
• Duesman Kevin G
• Mathew James
• Violette Michael P

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H01L27/11556

  Electricity · mapped topic

• H01L25/105 Primary

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H10B41/41 Primary

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title