Semiconductor device in a level shifter with electrostatic discharge (esd) protection circuit and semiconductor chip

Patent metadata

Field	Value
Publication number	US-2018358349-A1
Application number	US-201816050523-A
Country	US
Kind code	A1
Filing date	Jul 31, 2018
Priority date	Mar 13, 2015
Publication date	Dec 13, 2018
Grant date	—

Abstract

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a gate dielectric layer formed on a substrate; a gate electrode comprising a non-silicide region and a silicide region, and formed on the gate dielectric layer; and a source region and a drain region formed in the substrate, wherein the non-silicide region has an area larger than an area of the silicide region.

2 . A semiconductor device of claim 1 , wherein the source and drain regions each are respectively disposed next to the non-silicide region and spaced apart from the silicide region.

3 . A semiconductor device of claim 1 , wherein the non-silicide region extends from one end of the gate electrode and to the other end of the gate electrode.

4 . A semiconductor device of claim 1 , wherein the non-silicide region is in direct contact with the silicide region.

5 . A semiconductor device of claim 1 , further comprising a silicide blocking layer formed on the non-silicide region.

6 . A semiconductor device of claim 1 , wherein the non-silicide region overlaps with the drain region and the source region.

7 . A semiconductor device of claim 1 , further comprising a contact region formed in the silicide region.

8 . A semiconductor device of claim 1 , wherein the gate dielectric layer comprises a thin gate insulation layer and a thick gate insulation layer, and
wherein the non-silicide region overlaps with the thin gate insulation layer and the thick gate insulation layer.

9 . A semiconductor device of claim 8 , further comprising an extended drain junction region formed in the substrate,
wherein the extended drain junction region overlaps with the gate electrode and extends to a portion of the substrate under the thin gate insulation layer.

10 . A semiconductor device, comprising:
a gate dielectric layer formed on a substrate; a non-silicided poly-silicon layer formed on the gate dielectric layer; a silicided poly-silicon layer formed adjacent to the non-silicided poly-silicon layer; a gate contact region formed in the silicided poly-silicon layer; and a source region and a drain region formed in the substrate, wherein the non-silicided poly-silicon layer overlaps with the gate dielectric layer.

11 . A semiconductor device of claim 10 , wherein the non-silicided poly-silicon layer has an area larger than an area of the silicided poly-silicon layer.

12 . A semiconductor device of claim 10 , wherein the source region comprises a silicide region and a non-silicide region.

13 . A semiconductor device of claim 10 ,
wherein the gate dielectric layer comprises a thin gate insulation layer and a thick gate insulation layer, and wherein the non-silicided poly-silicon layer overlaps with the thin gate insulation layer and the thick gate insulation layer.

14 . A semiconductor device, comprising:
a gate dielectric layer formed on a substrate; a gate electrode comprising a high-resistance region and a low-resistance region, and formed on the gate dielectric layer; and a source region and a drain region formed in the substrate, wherein the high-resistance region has an area larger than an area of the low-resistance region.

15 . A semiconductor device of claim 14 , wherein the high-resistance region comprises a non-silicided poly-silicon layer, and wherein the low-resistance region comprises a silicided poly-silicon layer.

16 . A semiconductor device of claim 14 , wherein the source region comprises a silicide region and a non-silicide region.

17 . A semiconductor device of claim 14 , wherein the high-resistance region overlaps with the gate dielectric layer, and wherein the low-resistance region does not overlap with the gate dielectric layer.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hwang Kyong Jin
• Jeong Hyun Kwang

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H03K19/018507

  Interface arrangements · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H01L29/861

  Electricity · mapped topic