Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip

Patent metadata

Field	Value
Publication number	US-10068892-B2
Application number	US-201715626263-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Mar 13, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

The present disclosure relates to a semiconductor chip having a level shifter with electro-static discharge (ESD) protection circuit and device applied to multiple power supply lines with high and low power input to protect the level shifter from the static ESD stress. More particularly, the present disclosure relates to a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device.

First claim

What is claimed is:

1. A semiconductor device in a level shifter, comprising:
a gate insulating layer comprising a thin gate insulation layer and a thick gate insulation layer formed on a substrate;
a gate electrode formed on the thin gate insulation layer and on the thick gate insulation layer;
a non-silicide region, a silicide region, and a gate contact region formed on the gate electrode;
wherein the gate contact region does not overlap the thick gate insulation layer.

2. A semiconductor device in a level shifter of claim 1 , further comprising:
a drain region disposed adjacent to the thick gate insulation layer;
a source region disposed adjacent to the thin gate insulation layer; and
an extended drain junction region of a second conductivity type formed in a well region of a first conductivity type,
wherein the extended drain junction region overlaps with the gate electrode and extends to a portion of the well region under the thin gate insulating layer, and
the first conductivity type is an opposite type from the second conductivity type.

3. A semiconductor device in a level shifter of claim 1 , wherein the non-silicide region has a higher resistance than the silicide region.

4. A semiconductor device in a level shifter of claim 1 , wherein the non-silicide region comprises a silicide blocking layer.

5. A semiconductor device in a level shifter of claim 1 , wherein the gate electrode comprises a counter doped region.

6. A semiconductor device in a level shifter of claim 1 , wherein the non-silicide region of the gate electrode comprises a poly-silicon resistor.

7. A semiconductor device in a level shifter of claim 1 , wherein the gate contact region is in direct contact with the non-silicide region.

8. A semiconductor device in a level shifter, comprising:
a gate insulation layer comprising a thin gate insulation layer and a thick gate insulation layer formed on a substrate;
a silicided poly-silicon layer formed on the thin gate insulation layer and on the thick gate insulation layer;
a non-silicided poly-silicon layer formed adjacent to the silicided poly-silicon layer; and
a gate contact region formed adjacent to the non-silicided poly-silicon layer,
wherein the silicided poly-silicon layer is electrically connected to the non-silicided poly-silicon layer.

9. A semiconductor device in a level shifter of claim 8 , wherein the silicided poly-silicon layer and the non-silicided poly-silicon layer are electrically connected to each other through a metal connector.

10. A semiconductor device in a level shifter of claim 8 , wherein the gate contact region is in direct contact with the non-silicided poly-silicon layer.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hwang Kyong Jin
• Jeong Hyun Kwang

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03K19/018507

  Interface arrangements · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H01L29/861

  Electricity · mapped topic