Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip

Patent metadata

Field	Value
Publication number	US-9721941-B2
Application number	US-201514803976-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Mar 13, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

The present examples relate to a semiconductor chip having a level shifter with an electrostatic discharge (ESD) protection circuit and a device applying to multiple power supply lines with high and low power inputs to protect the level shifter from the static ESD stress. More particularly, the present examples relate to using a feature to protect a semiconductor device in a level shifter from the ESD stress by using ESD stress blocking region adjacent to a gate electrode of the semiconductor device. The ESD stress blocking region increases a gate resistance of the semiconductor device, which results in reducing the ESD stress applied to the semiconductor device itself.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a first input pad and a first ground pad located in a low voltage region on a semiconductor substrate;
a second input pad, and a second ground pad located in a high voltage region on the semiconductor substrate;
a first electrostatic discharge (ESD) clamp formed between the first input pad and the first ground pad; and
a level shifter comprising a semiconductor device and an ESD stress blocking region,
wherein the semiconductor device comprises a gate insulation layer having a thin gate insulation layer portion and a thick gate insulation layer portion, and a gate electrode formed over the gate insulation layer, and
wherein the ESD stress blocking region is electrically connected between the low voltage region and the gate electrode.

2. The semiconductor chip of claim 1 , wherein the ESD stress blocking region comprises a non-silicided polysilicon layer.

3. The semiconductor chip of claim 1 , further comprising:
a second ESD clamp connected between the second input pad and the second ground pad.

4. The semiconductor chip of claim 1 , wherein
the ESD stress blocking region protects the semiconductor device from Charged Device Model (CDM) ESD stress that occurs near the semiconductor device.

5. The semiconductor chip of claim 1 , wherein the ESD stress blocking region has a higher resistance than that of the gate electrode.

6. The semiconductor chip of claim 1 , wherein the ESD stress blocking region is connected to the gate electrode of the semiconductor device.

7. The semiconductor chip of claim 1 , wherein the first ESD clamp comprises a gate grounded N-channel Metal Oxide Semiconductor (NMOS).

8. The semiconductor chip of claim 1 , further comprising:
a back-to-back diode located between the first ground pad and the second ground pad.

9. The semiconductor chip of claim 1 , wherein the semiconductor device comprises an Extended Drain Metal Oxide Semiconductor (EDMOS) or a Laterally Diffused Metal Oxide Semiconductor (LDMOS); and
wherein the ESD stress blocking region is interconnected to the EDMOS or the LDMOS.

10. The semiconductor chip of claim 1 , further comprising:
a first path formed between the first input pad and the first ground pad; and
a second path formed between the first input pad and the second ground pad,
wherein the second path has higher resistance than the first path.

11. A semiconductor chip comprising:
a semiconductor substrate, comprising a first input pad and a first ground pad located in a low voltage region of the semiconductor substrate and a second input pad and a second ground pad located in a high voltage region of the semiconductor substrate;
a first electrostatic discharge (ESD) clamp located between the first input pad and the first ground pad; and
a level shifter comprising a semiconductor device comprising a gate insulator, comprising a thin gate insulation layer and a thick gate insulation layer, and a gate electrode formed over the gate insulator, and an ESD stress blocking region disposed between the low voltage region and the gate electrode.

12. The semiconductor chip of claim 11 , further comprising:
a second ESD clamp connected between the second input pad and the second ground pad.

13. The semiconductor chip of claim 11 , wherein the ESD stress blocking region has a higher resistance than that of the gate electrode.

14. The semiconductor chip of claim 11 , wherein the first ESD clamp comprises a gate grounded N-channel Metal Oxide Semiconductor (NMOS).

15. The semiconductor chip of claim 11 , wherein the semiconductor device comprises an Extended Drain Metal Oxide Semiconductor (EDMOS) or a Laterally Diffused Metal Oxide Semiconductor (LDMOS); and
wherein the ESD stress blocking region is interconnected to the EDMOS or the LDMOS.

16. The semiconductor chip of claim 11 , wherein the ESD stress blocking region is disposed between the low voltage region and the level shifter.

17. A semiconductor chip comprising:
a first input pad and a first ground pad located in a low voltage region on a semiconductor substrate;
a second input pad, and a second ground pad located in a high voltage region on the semiconductor substrate;
a first electrostatic discharge (ESD) clamp formed between the first input pad and the first ground pad; and
a level shifter comprising a semiconductor device and an ESD stress blocking region,
wherein the semiconductor device comprises a gate insulation layer having a thin gate insulation layer portion and a thick gate insulation layer portion, and a gate electrode formed over the gate insulation layer, and
wherein the ESD stress blocking region is directly electrically connected to the gate electrode.

Assignees

• Magnachip Semiconductor Ltd

Inventors

• Hwang Kyong Jin
• Jeong Hyun Kwang

Classifications

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title

• H03K19/00361

  in field effect transistor circuits · CPC title

• H03K19/018507

  Interface arrangements · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• H01L27/0629

  Electricity · mapped topic