Semiconductor device

US2018350974A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2018350974-A1
Application numberUS-201715830809-A
CountryUS
Kind codeA1
Filing dateDec 4, 2017
Priority dateJun 2, 2017
Publication dateDec 6, 2018
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

According to one embodiment, the insulating film is provided on a side surface of a second semiconductor layer located at an end in the lateral direction of the second semiconductor layers, or a side surface of a third semiconductor layer located at an end in the lateral direction of the third semiconductor layers. The semiconductive film is provided on a side surface of the insulating film. The semiconductive film is electrically connected to the first electrode and the second electrode. The semiconductive film has a resistivity higher than a resistivity of one of the second semiconductor layers and a resistivity of one of the third semiconductor layers, and lower than a resistivity of the insulating film.

First claim

Opening claim text (preview).

1 . A semiconductor device comprising: a first electrode; a second electrode; a first semiconductor layer having a first conductivity type and provided on the first electrode; a plurality of second semiconductor layers having the first conductivity type and provided on the first semiconductor layer, the plurality of second semiconductor layers extending in a vertical direction connecting the first electrode and the second electrode; a plurality of third semiconductor layers having a second conductivity type, the plurality of third semiconductor layers extending in the vertical direction on the first semiconductor layer, and adjacent to the plurality of second semiconductor layers in a lateral direction crossing the vertical direction; a fourth semiconductor layer having the second conductivity type and provided on one of the plurality of third semiconductor layers; a fifth semiconductor layer having the first conductivity type and provided on a surface of the fourth semiconductor layer, the fifth semiconductor layer connected to the second electrode; a gate electrode opposed to the fourth semiconductor layer; a gate insulating film provided between the fourth semiconductor layer and the gate electrode; an insulating film provided on a side surface of a second semiconductor layer located at an end in the lateral direction of the plurality of second semiconductor layers, or a side surface of a third semiconductor layer located at an end in the lateral direction of the plurality of third semiconductor layers; and a semiconductive film provided on a side surface of the insulating film, the semiconductive film electrically connected to the first electrode and the second electrode, the semiconductive film having a resistivity higher than a resistivity of one of the plurality of second semiconductor layers and a resistivity of one of the plurality of third semiconductor layers, and lower than a resistivity of the insulating film, the insulating film being provided between the semiconductive film and one of the second semiconductor layer located at the end or the third semiconductor layer located at the end, the semiconductive film not contacting the second semiconductor layer and the third semiconductor layer. 2 . The device according to claim 1 , wherein the semiconductive film has contact with the first semiconductor layer. 3 . The device according to claim 1 , wherein the fourth semiconductor layer has contact with the second electrode, and the semiconductive film has contact with the fourth semiconductor layer. 4 . The device according to claim 1 , wherein the insulating film continuously surrounds a region where the second semiconductor layers and the third semiconductor layers are disposed. 5 . The device according to claim 1 , wherein the semiconductive film continuously surrounds a region where the second semiconductor layers and the third semiconductor layers are disposed. 6 . The device according to claim 1 , wherein the semiconductive film is a silicon nitride film. 7 . The device according to claim 1 , wherein the semiconductive film is a polycrystalline silicon film. 8 . The device according to claim 1 , wherein the insulating film is a silicon oxide film. 9 . The device according to claim 1 , further comprising: resin provided on a side surface of the semiconductive film. 10 . The device according to claim 1 , wherein the insulating film is provided on a sidewall of a trench extending in the vertical direction to reach the first semiconductor layer, and the semiconductive film is provided on a side surface of the insulating film in the trench. 11 . The device according to claim 10 , further comprising: a sixth semiconductor layer provided outside the trench and on the first semiconductor layer. 12 . The device according to claim 11 , wherein the sixth semiconductor layer is a first conductivity type semiconductor layer. 13 . The device according to claim 10 , further comprising: an insulator provided inside the semiconductive film in the trench. 14 . The device according to claim 13 , wherein the insulator is a silicon oxide film. 15 . The device according to claim 1 , wherein a first conductivity type impurity concentration of the first semiconductor layer is higher than a first conductivity type impurity concentration of one of the plurality of second semiconductor layers. 16 . The device according to claim 1 , wherein a first conductivity type impurity concentration of the fifth semiconductor layer is higher than a first conductivity type impurity concentration of one of the plurality of second semiconductor layers. 17 . The device according to claim 1 , wherein the fourth semiconductor layer on a termination side extends to an end of the device.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2018350974A1 cover?
According to one embodiment, the insulating film is provided on a side surface of a second semiconductor layer located at an end in the lateral direction of the second semiconductor layers, or a side surface of a third semiconductor layer located at an end in the lateral direction of the third semiconductor layers. The semiconductive film is provided on a side surface of the insulating film. Th…
Who is the assignee on this patent?
Toshiba Kk, Toshiba Electronic Devices & Storage Corp
What technology area does this patent fall under?
Primary CPC classification H01L29/7811. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Dec 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).