Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

Patent metadata

Field	Value
Publication number	US-2018337129-A1
Application number	US-201515774937-A
Country	US
Kind code	A1
Filing date	Dec 11, 2015
Priority date	Dec 11, 2015
Publication date	Nov 22, 2018
Grant date	—

Abstract

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

First claim

1 - 25 . (canceled)

26 . A method of forming a microelectronic structure, comprising:
forming a first and a second microelectronic device, wherein each of the first and the second microelectronic device include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; attaching a microelectronic bridge to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; forming a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface; and electrically attaching the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device to the first surface of the microelectronic substrate, wherein the microelectronic bridge extends into the microelectronic substrate cavity.

27 . The method of claim 26 , wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device.

28 . The method of claim 26 , wherein the microelectronic bridge includes a plurality of conductive routes therein.

29 . The method of claim 26 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein.

30 . The method of claim 26 , further including disposing an underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity.

31 . The method of claim 26 , further comprising forming a reconstituted wafer from the first microelectronic device and the second microelectronic device prior to attaching the microelectronic bridge.

32 . The method of claim 31 , wherein forming the reconstituted wafer comprises disposing an encapsulant material between at least one side of the first microelectronic device and at least one side of the second microelectronic device.

33 . The method of claim 32 , further including aligning the first microelectronic device and the second microelectronic device on a carrier with the active surface of each of the first microelectronic device and the second device facing the carrier, and wherein disposing the encapsulant material comprises disposing the encapsulant material over a back surface of the first microelectronic device and a back surface of the second microelectronic device.

34 . The method of claim 33 , wherein aligning the first microelectronic device and the second microelectronic device on the carrier further comprises adhering the first microelectronic device and the second microelectronic device to the carrier with an adhesive layer.

35 . The method of claim 33 , further comprising removing a portion of the encapsulant material to expose the back surface of the first microelectronic device and the back surface of the second microelectronic device.

36 . The method of claim 35 , further comprising removing a portion of the in the first microelectronic device and the second microelectronic device.

37 . The method of claim 26 , wherein attaching the microelectronic bridge to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device comprises aligning a back surface of each of the first microelectronic device and the second microelectronic device on a carrier and attaching the microelectronic bridge.

38 . The method of claim 37 , further comprising disposing a flux material on the plurality of high density interconnect surface of the first microelectronic device and on the plurality of high density interconnect surface of the second microelectronic device; and attaching the microelectronic bridge through the flux material.

39 . A microelectronic structure comprising:
a first and a second microelectronic device, wherein each of the first and the second microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof, a microelectronic bridge attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity; and an underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity.

40 . The microelectronic structure of claim 39 , wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device.

41 . The microelectronic structure of claim 39 , wherein the microelectronic bridge includes a plurality of conductive routes therein.

42 . The microelectronic structure of claim 39 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein.

43 . The microelectronic structure of claim 39 , further comprising a reconstituted wafer formed from the first microelectronic device and the second microelectronic device.

44 . The microelectronic structure of claim 43 , wherein the reconstituted wafer includes an encapsulant material between at least one side of the first microelectronic device and at least one side of the second microelectronic device.

45 . The microelectronic structure of claim 39 , further comprising a flux material disposed between the first microelectronic device and the microelectronic bridge, and between on the second microelectronic device and the microelectronic bridge.

46 . A computing device, comprising:
a board; a microelectronic structure attached to the board, wherein the microelectronic structure comprises:
a first and a second microelectronic device, wherein each of the first and the second microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof;
a microelectronic bridge attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device;
a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surfa

Assignees

• Intel Corp

Inventors

• Li Eric J
• Gosselin Timothy A
• Tomita Yoshihiro
• Liff Shawna M
• Eitan Amram
• Saltas Mark

Classifications

• H10W72/551

  Materials of bond wires · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title