Nonvolatile Digital Computing with Ferroelectric FET

Patent metadata

Field	Value
Publication number	US-2018330791-A1
Application number	US-201815976315-A
Country	US
Kind code	A1
Filing date	May 10, 2018
Priority date	May 11, 2017
Publication date	Nov 15, 2018
Grant date	—

Abstract

Embodiments include nonvolatile a memory (NVM) device that can be configured for logic switching and/or digital computing. For example, embodiments of the NVM device can be configured as any one or combination of a memory cell, a D flip flop (DFF), a Backup and Restore circuit (B&R circuit), and/or a latch for a DFF. Any of the NVM devices can have a Fe field effect transistors (FeFET) configured to exploit the I DS −V G hysteresis of the steep switch at low voltage for logic memory synergy. The FeFET-based devices can be configured to include a wide hysteresis, a steep hysteresis edge, and high ratio between the two I DS states at V G =0.

First claim

We claim:

1 . A nonvolatile memory (NVM) device, comprising a circuit topology having at least one Fe field effect transistor (FeFET) configured to exhibit a wide current-voltage (I-V) hysteresis covering zero gate bias.

2 . The NVM device recited in claim 1 , wherein:
the circuit topology is configured as a backup and restore circuit (B&R circuit); the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a first branch and a second branch, the first branch including M 1 , M 2 , M 5 , M 7 , and a ground, GND, the second branch including M 3 , M 4 , M 6 , and M 8 ;
each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M 5 and M 6 is a FeFET;
M 1 -gate being connected to a backup control signal input, B kp _ input and M 3 -gate;
M 1 -drain being connected to M 2 -drain;
M 1 -drain being configured to be connected to a slave latch via the first branch;
M 1 -source being connected to M 5 -source and M 7 -drain;
M 2 -drain being connected to M 1 -drain;
M 2 -drain being configured to be connected to the slave latch via the first branch;
M 2 -gate being connected to a backup and restore control signal input, B kp +R str and M 3 -gate;
M 2 -source being connected to M 6 -gate, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 3 -drain being connected to M 4 -drain;
M 3 -drain being configured to be connected to the slave latch via the second branch;
M 3 -gate being connected to B kp +R str and M 1 -gate;
M 3 -source being connected to M 5 -gate, M 6 -drain, M 5 -drain, M 2 -source, and M 6 -gate;
M 4 -drain being connected to M 3 -drain;
M 4 -drain being configured to be connected to the slave latch via the second branch;
M 4 -gate being connected to a backup control signal output, B kp _ output ;
M 4 -source being connected to M 6 -source and M 8 -drain;
M 5 -drain being connected to M 2 -source, M 5 -gate, M 6 -gate, M 6 -drain, and M 3 -source;
M 5 -gate being connected to M 3 -source, M 6 -drain, M 6 -gate, M 2 -source, and M 5 -drain;
M 5 -source being connected to M 7 -drain and M 1 -source;
M 6 -drain being connected to M 3 -source, M 5 -gate, M 6 -gate, M 5 -drain, and M 2 -source;
M 6 -gate being connected to M 2 -source, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 6 -source being connected to M 4 -source and M 8 -drain;
M 7 -drain being connected to M 1 -source and M 5 -source;
M 7 -gate being connected to a restore input control signal, R str ;
M 7 -source being connected to GND via the first branch;
M 8 -drain being connected to M 4 -source and M 6 -source;
M 8 -gate being connected to M 7 -gate; and
M 8 -source being connected to GND via the second branch.

3 . The NVM device recited in claim 1 , wherein:
the circuit topology is configured as a D-Flip Flop (DFF); the DFF comprising a master latch, a slave latch, and a backup and restore circuit (B&R circuit); the master latch comprising:
a first master inverter M INV1 , a second master inverter, M INV2 , a third master inverter, M INV3 , and a master transmission gate, M GATE ;
input of M INV1 being connected to a data input signal, D;
output of M INV1 being connected to input of M INV2 ;
input of M INV2 being connected to output of M INV1 ;
output of M INV2 being connected to input of M INV3 ;
input of M INV3 being connected to output of M INV2 ;
output of M INV3 being connected to input of M GATE ;
input of M GATE being connected to output of M INV3 ; and
output of M GATE being connected to input of M INV2 and output of M INV1 ;
the slave latch comprising:
a first slave inverter, S INV1 , a second slave inverter, S INV2 , a third slave inverter, S INV3 , and a slave transmission gate, S GATE ;
input of S INV1 being connected to output of M INV2 ;
input of S INV2 being connected to output of S INV1 ;
output of S INV2 being connected to input of S INV3 and to a data output Q;
input of S INV3 being connected to output of S INV2 ;
output of S INV3 being connected to input of S GATE ; and
output of S GATE being connected to input of S INV2 and output of S INV1 ; and
the B&R circuit comprising:
a first transistor, M 1 , M 1 having an M 1 -source, an M 1 -gate, and an M 1 -drain;
a second transistor, M 2 , M 2 having an M 2 -source, an M 2 -gate, and an M 2 -drain;
a third transistor, M 3 , M 3 having an M 3 -source, an M 3 -gate, and an M 3 -drain;
a fourth transistor, M 4 , M 4 having an M 4 -source, an M 4 -gate, and an M 4 -drain;
a fifth transistor, M 5 , M 5 having an M 5 -source, an M 5 -gate, and an M 5 -drain;
a sixth transistor, M 6 , M 6 having an M 6 -source, an M 6 -gate, and an M 6 -drain;
a seventh transistor, M 7 , M 7 having an M 7 -source, an M 7 -gate, and an M 7 -drain;
an eighth transistor, M 8 , M 8 having an M 8 -source, an M 8 -gate, and an M 8 -drain;
a first branch and a second branch, the first branch including M 1 , M 2 , M 5 , M 7 , and a ground, GND, the second branch including M 3 , M 4 , M 6 , and M 8 ;
each of M 1 , M 2 , M 3 , M 4 , M 7 , and M 8 is a metal-oxide-semiconductor field-effect transistor (MOSFET) and each of M 5 and M 6 is a FeFET;
M 1 -gate is connected to a backup control signal input, B kp _ input and M 3 -gate;
M 1 -drain is connected to M 2 -drain;
M 1 -drain is configured to be connected to the slave latch via the first branch;
M 1 -source is connected to M 5 -source and M 7 -drain;
M 2 -drain is connected to M 1 -drain;
M 2 -drain is configured to be connected to the slave latch via the first branch;
M 2 -gate is connected to a backup and restore control signal input, B kp +R str and M 3 -gate;
M 2 -source is connected to M 6 -gate, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 3 -drain is connected to M 4 -drain;
M 3 -drain is configured to be connected to the slave latch via the second branch;
M 3 -gate is connected to B kp +R str and M 1 -gate;
M 3 -source is connected to M 5 -gate, M 6 -drain, M 5 -drain, M 2 -source, and M 6 -gate;
M 4 -drain is connected to M 3 -drain;
M 4 -drain is configured to be connected to the slave latch via the second branch;
M 4 -gate is connected to a backup control signal output, B kp _ output ,
M 4 -source is connected to M 6 -source and M 8 -drain;
M 5 -drain is connected to M 2 -source, M 5 -gate, M 6 -gate, M 6 -drain, and M 3 -source;
M 5 -gate is connected to M 3 -source, M 6 -drain, M 6 -gate, M 2 -source, and M 5 -drain;
M 5 -source is connected to M 7 -drain and M 1 -source;
M 6 -drain is connected to M 3 -source, M 5 -gate, M 6 -gate, M 5 -drain, and M 2 -source;
M 6 -gate is connected to M 2 -source, M 5 -drain, M 5 -gate, M 6 -drain, and M 3 -source;
M 6 -source is connected to M 4 -source and M 8 -drain;
M 7 -drain is connected to M 1 -source and M 5 -source;
M 7 -gate is connected to a restore input control signal, R str ;
M 7 -source is connected to GND via the first branch;
M 8 -drain is connected to M 4 -source and M 6 -source;
M 8 -gate is connected to M 7 -gate; and
M 8 -source is connected to GND via the second branch.

Assignees

• Penn State Res Found

Inventors

• Li Xueqing
• George Sumitha
• SAMPSON John
• Gupta Sumeet
• Datta Suman
• Narayanan Vijaykrishnan
• Ma Kaisheng

Classifications

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C14/0081

  and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C11/2293

  Timing circuits or methods · CPC title