Simple cmos threshold voltage extraction circuit

Patent metadata

Field	Value
Publication number	US-2018307262-A1
Application number	US-201715497051-A
Country	US
Kind code	A1
Filing date	Apr 25, 2017
Priority date	Apr 25, 2017
Publication date	Oct 25, 2018
Grant date	—

Abstract

The disclosure is directed to a simple, inexpensive circuit to extract the complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) from an integrated circuit. The threshold voltage may be used elsewhere in the circuit for a variety of purposes. One example use of threshold voltage is to sense the temperature of the circuit. The CMOS Vt extraction circuit of this disclosure includes a current mirror and an arrangement of well-matched transistors and resistors that takes advantage of the square law equation. The structure of the circuit may make it well suited to applications that benefit from low-power radiation hardened circuits.

First claim

1 : A circuit comprising:
first circuitry comprising a first current mirror; a first resistor; and a second resistor, wherein the first resistor and the second resistor are substantially matched; second circuitry comprising a second current mirror, wherein:
the second current mirror comprises a first transistor and a second transistor,
a width-to-length ratio of the second transistor is greater than a width-to-length ratio of the first transistor,
the circuit is configured to cause a first current through the first transistor to be substantially equal to a second current through the second transistor and to cause the second current to pass through the first resistor; and
a third transistor, wherein:
the second transistor and the third transistor are substantially matched,
the circuit is configured to cause a third current through the third transistor to be substantially equal to the second current through the second transistor and to cause the third current to pass through the second resistor, and
a gate-drain voltage of the third transistor is substantially equal to a voltage across the second resistor;
an output interface configured to output a drain-source voltage across the third transistor.

2 : The circuit of claim 1 , wherein the width-to-length ratio of the second transistor is approximately four times greater than the width-to-length ratio of the first transistor.

3 : The circuit of claim 1 , wherein a gate-source voltage of the first transistor approximately equals a sum of a voltage across the first resistor plus a gate-source voltage of the second transistor.

4 : The circuit of claim 1 , wherein:
the first current mirror comprises pMOS transistors; the second circuitry and the third transistor comprise nMOS transistors.

5 : The circuit of claim 1 , wherein:
the first current mirror comprises nMOS transistors; the second circuitry and the third transistor comprise pMOS transistors.

6 : The circuit of claim 1 , wherein the circuit is configured to cause a gate-source voltage of the second transistor to be substantially equal to a sum of the voltage across the second resistor plus the drain-source voltage of the third transistor.

7 : The circuit of claim 1 , wherein the first current mirror comprises a first leg, a second leg and a third leg, and wherein
the first current comprises a current through the first leg, the second current comprises a current through the second leg, the third current comprises a current through the third leg.

8 : The circuit of claim 7 , wherein the third leg comprises a fourth transistor and a gate of the third transistor connects to a node between the second resistor and the fourth transistor.

9 : The circuit of claim 1 , wherein the drain-source voltage across the third transistor is a CMOS threshold voltage.

10 : A system comprising,
a complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt) extraction circuit, the Vt extraction circuit comprising:
a first circuitry, comprising a first current mirror;
a first resistor; and
a second resistor, wherein the first resistor and the second resistor are substantially matched;

a second circuitry comprising a second current mirror, wherein:
the second current mirror comprises a first transistor and a second transistor,
a width-to-length ratio of the second transistor is greater than a width-to-length ratio of the first transistor,
the circuit is configured to cause a first current through the first transistor to be substantially equal to a second current through the second transistor and to cause the second current to pass through the first resistor; and

a third transistor, wherein:
the second transistor and the third transistor are substantially matched,
the circuit is configured to:
cause a third current through the third transistor to be substantially equal to the second current through the second transistor;
cause the third current to pass through the second resistor,
cause a first output voltage of the Vt extraction circuit to be a drain-source voltage across the third transistor; and
cause a gate-drain voltage of the third transistor to be substantially equal to a voltage across the second resistor;

an output leg, the output leg comprising:
a resistance substantially equal to twice a resistance of the first resistor, wherein the circuit is configured to cause a fourth current through the resistance to be substantially equal to the first current;
a second output voltage, wherein the second output voltage comprises a voltage proportional to absolute temperature (V_PTAT).

11 : The system of claim 10 , wherein the first output voltage is a CMOS threshold voltage.

12 : The system of claim 10 , wherein the width-to-length ratio of the second transistor is approximately four times greater than the width-to-length ratio of the first transistor.

13 : The system of claim 10 , wherein the Vt extraction circuit is configured to cause a gate-source voltage of the first transistor to approximately equal a sum of a voltage across the first resistor plus a gate-source voltage of the second transistor.

14 : The system of claim 10 , wherein:
the first current mirror comprises pMOS transistors; the second circuitry and the third transistor comprise nMOS transistors.

15 : The system of claim 10 , wherein:
the first current mirror comprises nMOS transistors; the second circuitry and the third transistor comprise pMOS transistors.

16 : The system of claim 10 , wherein the Vt extraction circuit is configured to cause a gate-source voltage of the second transistor to be substantially equal to a sum of a drain-source voltage of the third transistor plus a voltage across the second resistor.

17 : A method of determining a complementary metal-oxide-semiconductor (CMOS) threshold voltage (Vt), the method comprising:
directing a first current through a first transistor; directing a second current through a second transistor, wherein:
the second current is substantially equal to the first current,
the second current passes through a first resistor connected in series to the second transistor, and
the second transistor and the first resistor are configured such that a gate-source voltage of the first transistor equals a sum of a voltage across the first resistor plus a gate-source voltage of the second transistor;
directing a third current through a third transistor, wherein:
the third current is substantially equal to the first current,
the third current passes through a second resistor connected to the third transistor, and
the gate-source voltage of the second transistor is substantially equal to a sum of a drain-source voltage across the third transistor plus a voltage across the second resistor,
a gate-drain voltage of the third transistor is substantially equal to a voltage across the second resistor,
the third transistor and the second transistor are substantially matched, and
the second resistor and the first resistor are substantially matched; and
determining the drain-source voltage of the third transistor.

18 : The method of claim 17 , wherein a width-to-length ratio of the second transistor is approximately four times greater than a width-to-length ratio of the first transistor.

19 : The method of claim 17 , wherein a current mirror directs the first current the first current through the first transistor, the second current through the second transistor and the third current through the third transistor.

20 : The method

Assignees

• Honeywell Int Inc

Inventors

• Feng Xiaoxin
• Roper Weston

Classifications

• H03K17/0822

  in field-effect transistor switches · CPC title

• G05F3/26

  Current mirrors · CPC title

• G05F1/10

  Regulating voltage or current  (G05F1/02 takes precedence) · CPC title

• H03K19/00384

  in field effect transistor circuits · CPC title

• G05F3/242 Primary

  with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage · CPC title