Task latency debugging in symmetric multiprocessing computer systems

Patent metadata

Field	Value
Publication number	US-2018285147-A1
Application number	US-201715478379-A
Country	US
Kind code	A1
Filing date	Apr 4, 2017
Priority date	Apr 4, 2017
Publication date	Oct 4, 2018
Grant date	—

Abstract

An aspect includes performing, for each of a plurality of hardware threads executing on a plurality of cores in a (SMP) computer system, receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer. The value of the timer is compared to a threshold value for the hardware thread, where the threshold value specifies a number of clock cycles. Based on the value of the timer meeting the threshold value, a control signal is sent to cause all hardware threads currently executing on the core to halt execution and data describing a state of the core is logged. Each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

First claim

What is claimed is:

1 . A method comprising:
for each of a plurality of hardware threads executing on a plurality of cores in a symmetric multiprocessing (SMP) computer system:
receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer;
comparing the value of the timer to a threshold value for the hardware thread, the threshold value specifying a number of clock cycles; and
based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the core to halt execution; and
logging data describing a state of the core,

wherein each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

2 . The method of claim 1 , further comprising, based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the SMP computer system to halt execution; and logging data describing a state of the SMP computer system including the state of the core.

3 . The method of claim 1 , further comprising for each of the plurality of hardware threads, prior to receiving the value of the timer:
determining an address of a next instruction to be executed on the hardware thread; comparing the address of the next instruction to a starting address of interest; resuming the timer based on the address of the next instruction being the same as the starting address of interest; comparing the address of the next instruction to an ending address of interest; resetting the timer based on the address of the next instruction being the same as the ending address of interest.

4 . The method of claim 1 , wherein firmware located on the core resets the timer periodically.

5 . The method of claim 1 , wherein the timer is reset in response to an instruction executing on the hardware thread completing.

6 . The method of claim 1 , further comprising:
pausing the timer in response to detecting a stall event; and restarting the timer in response to detecting that the stall event has completed.

7 . The method of claim 1 , further comprising restarting execution of the halted hardware thread on the core in response to the logging completing.

8 . A system comprising:
a memory having computer readable instructions; and one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising: for each of a plurality of hardware threads executing on a plurality of cores in a symmetric multiprocessing (SMP) computer system:
receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer;
comparing the value of the timer to a threshold value for the hardware thread, the threshold value specifying a number of clock cycles; and
based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the core to halt execution; and
logging data describing a state of the core,

wherein each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

9 . The system of claim 8 , wherein the operations further comprise, based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the SMP computer system to halt execution; and logging data describing a state of the SMP computer system including the state of the core.

10 . The system of claim 8 , wherein the operations further comprise for each of the plurality of hardware threads, prior to receiving the value of the timer:
determining an address of a next instruction to be executed on the hardware thread; comparing the address of the next instruction to a starting address of interest; resetting the timer based on the address of the next instruction being the same as the starting address of interest; comparing the address of the next instruction to an ending address of interest; resetting the timer based on the address of the next instruction being the same as the ending address of interest.

11 . The system of claim 8 , wherein firmware located on the core resets the timer periodically.

12 . The system of claim 8 , wherein the timer is reset in response to an instruction executing on the hardware thread completing.

13 . The system of claim 8 , wherein the operations further comprise:
pausing the timer in response to detecting a stall event; and restarting the timer in response to detecting that the stall event has completed.

14 . The system of claim 8 , wherein the operations further comprise restarting execution of the halted hardware thread on the core in response to the logging completing.

15 . A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
for each of a plurality of hardware threads executing on a plurality of cores in a symmetric multiprocessing (SMP) computer system:
receiving a value of a timer corresponding to the hardware thread, the timer counting a number of clock cycles since a last reset of the timer;
comparing the value of the timer to a threshold value for the hardware thread, the threshold value specifying a number of clock cycles; and
based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the core to halt execution; and
logging data describing a state of the core,

wherein each of the timers corresponding to each of the plurality of hardware threads are configured to be reset, paused, and restarted independently of each of the other timers.

16 . The computer program product of claim 15 , wherein the operations further comprise, based on the value of the timer meeting the threshold value:
sending a control signal to cause all hardware threads currently executing on the SMP computer system to halt execution; and logging data describing a state of the SMP computer system including the state of the core.

17 . The computer program product of claim 15 , wherein the operations further comprise for each of the plurality of hardware threads, prior to receiving the value of the timer:
determining an address of a next instruction to be executed on the hardware thread; comparing the address of the next instruction to a starting address of interest; resetting the timer based on the address of the next instruction being the same as the starting address of interest; comparing the address of the next instruction to an ending address of interest; resetting the timer based on the address of the next instruction being the same as the ending address of interest.

18 . The computer program product of claim 15 , wherein firmware located on the core resets the timer periodically.

19 . The computer program product of claim 15 , wherein the timer is reset in response to an instruction executing on the hardware thread completing.

20 . The computer program product of claim 15 , wherein the operations furth

Assignees

• IBM

Inventors

• Engler Eberhard
• Jacobi Christian
• Slegel Timothy J
• Swaney Scott B

Classifications

• G06F2201/81

  Threshold · CPC title

• G06F11/0757

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title

• G06F11/362 Primary

  Debugging of software · CPC title

• G06F11/0778

  Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

• G06F9/485 Primary

  Task life-cycle, e.g. stopping, restarting, resuming execution (G06F9/4881 takes precedence) · CPC title