Magnetoelectric Computational Devices

Patent metadata

Field	Value
Publication number	US-2018248554-A1
Application number	US-201815959700-A
Country	US
Kind code	A1
Filing date	Apr 23, 2018
Priority date	Jul 19, 2016
Publication date	Aug 30, 2018
Grant date	—

Abstract

Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition.

First claim

1 . A semiconductor device comprising:
a first logic device comprising:
a first input electrode and a first ground electrode configured to produce an electric field within a first layer of antiferromagnetic material when a voltage is applied to the first input electrode relative to the first ground electrode, wherein the first layer of antiferromagnetic material produces a magnetic field in response to an application of an electric field;
a first set of a first free magnet and a second free magnet, wherein the first set of first and second free magnets are separated by a first isolation layer, wherein the first set first free magnet is in magnetic communication with the first layer of antiferromagnetic material, and wherein the first set second free magnet is in magnetic communication with the first set first free magnet;
a first permanent magnet separated from the first set second free magnet by a second isolation layer;
a first digital voltage electrode in electrical communication with the first permanent magnet; and
a first output electrode in electrical communication with the first set second free magnet.
a second logic device comprising:
a second input electrode and a second ground electrode configured to produce an electric field within a second layer of antiferromagnetic material when a voltage is applied to the second input electrode relative to the second ground electrode, wherein the second layer of antiferromagnetic material produces a magnetic field in response to an application of an electric field;
a second set of a first free magnet and a second free magnet, wherein the second set of first and second free magnets are separated by a third isolation layer, wherein the second set first free magnet is in magnetic communication with the second layer of antiferromagnetic material, and wherein the second set second free magnet is in magnetic communication with the second set first free magnet;
a second permanent magnet separated from the second set second free magnet by a fourth isolation layer;
a second digital voltage electrode in electrical communication with the second set second permanent magnet; and
a second output electrode in electrical communication with the second set second free magnet;
wherein the first input electrode is in electrical communication with the first antiferromagnetic layer, and the first ground electrode is in electrical communication with the first set first free magnet; wherein the second input electrode is in electrical communication with the second set first free magnet, and the second ground electrode is in electrical communication with the second antiferromagnetic layer; and wherein the first output electrode is in electrical communication with the second output electrode.

2 . The semiconductor device of claim 1 , wherein the semiconductor device is configured such that when a first digital voltage applied to the first input electrode, and a second digital voltage applied to the second input electrode, wherein the first digital voltage has an opposite polarity than the second digital voltage relative to ground, electrical fields with opposite directions are generated across the first and second layers of antiferromagnetic material, and switch the first and second sets of first free magnets to opposite orientations.

3 . The semiconductor device of claim 1 , wherein the first and second set second free magnets are magnetically coupled to the respective first and second set first free magnets;
wherein the first permanent magnet is in contact with the second isolation layer; wherein the second permanent magnet is in contact with the fourth isolation layer; wherein the second isolation layer is in contact with the first set second free magnet; and wherein the fourth isolation layer is in contact with the second set second free magnet.

4 . The semiconductor device of claim 1 , wherein the first set second free magnet is coupled to the first set first free magnet by exchange coupling.

5 . The semiconductor device of claim 1 , wherein the second set second free magnet is coupled to the second set first free magnet by exchange coupling.

6 . The semiconductor device of claim 1 , wherein the first set second free magnet is coupled to the first set first free magnet by dipole coupling.

7 . The semiconductor device of claim 1 , wherein the second set second free magnet is coupled to the second set first free magnet by dipole coupling.

8 . The semiconductor device of claim 1 , wherein the first isolation layer has a thickness selected to suppress leakage current from the first input electrode to the first ground electrode.

9 . The semiconductor device of claim 1 , wherein the third isolation layer has a thickness selected to suppress leakage current from the second input electrode to the second ground electrode.

10 . The semiconductor device of claim 1 , wherein the second isolation layer has a thickness selected to permit electron tunneling between the first input electrode and the first output electrode when the polarity of the first set first permanent magnet and the first set second free magnet are similarly directed.

11 . The semiconductor device of claim 1 , wherein the fourth isolation layer has a thickness selected to permit electron tunneling between the second input electrode and the second output electrode when the polarity of the second set first permanent magnet and the second set second free magnet are similarly directed.

12 . The semiconductor device of claim 1 , wherein thicknesses of the first and third isolation layers are each approximately two times to three times a thickness of the second and fourth isolation layers, respectively.

13 . The semiconductor device of claim 1 , wherein each of the first and second set of first permanent magnets comprise:
a layer comprised, at least in part, of an alloy of cobalt and iron; and a layer comprised, at least in part, of an alloy of iridium and magnesium.

14 . The semiconductor device of claim 1 , wherein each of the first and second antiferromagnetic layers comprise a material selected from the group consisting of chromium oxide, bismuth ferrite, and combinations thereof.

15 . The semiconductor device of claim 1 , wherein each of the first and second set first free magnets comprise a material selected from the group consisting of cobalt iron alloys, cobalt palladium alloys, lanthanum strontium manganite, and combinations thereof.

16 . The semiconductor device of claim 1 , wherein each of the first and third isolation layers comprise a material selected from the group consisting of magnesium oxide, yttrium-aluminum-garnet, iron oxide, and combinations thereof.

17 . The semiconductor device of claim 1 , wherein each of the second and fourth isolation layers comprise a material selected from the group consisting of magnesium oxide, aluminum oxide, and combinations thereof.

Assignees

• Georgia Tech Res Inst

Inventors

• Pan Chenyun
• Dutta Sourav
• Naeemi Azad

Classifications

• H01F10/3218

  Exchange coupling of magnetic films via an antiferromagnetic interface (H01F10/3268 takes precedence) · CPC title

• H01F10/16

  containing cobalt ({H01F10/126} , H01F10/13 take precedence) · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L27/22

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic