Magnetoelectric computational devices

Patent metadata

Field	Value
Publication number	US-9979401-B2
Application number	US-201715654278-A
Country	US
Kind code	B2
Filing date	Jul 19, 2017
Priority date	Jul 19, 2016
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes, and prevents the racing condition.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a logic component, comprising:
an input electrode and a ground electrode configured to produce an electric field within a layer of antiferromagnetic material that produces a magnetic field in response to the application of an electric field,
a free magnet and a permanent magnet, wherein the free magnet and permanent magnet are separated by a magnet isolation layer, wherein the free magnet is in magnetic communication with the layer of antiferromagnetic material and
an output electrode in electric communication with the permanent magnet;

a bias component, comprising:
a first pre-set electrode and a second pre-set electrode configured to produce an electric field within a layer of antiferromagnetic material that produces a magnetic field in response to the application of an electric field,
a free magnet and a permanent magnet, wherein the free magnet and the permanent magnet are separated by a magnet isolation layer, wherein the free magnet is in magnetic communication with the layer of antiferromagnetic material, and
an output electrode in electric communication with the permanent magnet,
wherein the output electrode of the bias component is in electrical communication with the output electrode of the logic component;

wherein the logic component is configured to be pre-set by applying a ground voltage to the first pre-set electrode and a pre-set voltage to the second pre-set electrode;
wherein the logic component is configured to be operable by applying an operating voltage to the second pre-set electrode, and a voltage approximately double the operating voltage to the first pre-set electrode, wherein the operating voltage has an opposite polarity from the pre-set voltage.

2. The semiconductor device of claim 1 , wherein the permanent magnet and free magnet of the bias component have parallel polarities.

3. The semiconductor device of claim 2 , wherein the operating voltage is selected to bias the free magnet of the logic component to have a polarity opposite to the polarization of the permanent magnet of the logic component present when no input is applied to the logic component.

4. The semiconductor device of claim 1 , wherein pre-setting the logic component comprises magnetizing the first free magnet of the logic component.

5. The semiconductor device of claim 1 , wherein the logic component of the semiconductor device further comprises a second input electrode configured to produce an electric field within the layer of antiferromagnetic material of the logic component when a voltage is applied to the second input electrode relative to ground.

6. The semiconductor device of claim 1 , wherein the input electrode of the logic component is in electric communication with the free magnet of the logic component, and wherein the ground electrode of the logic component is in electric communication with the antiferromagnetic layer of the logic component.

7. The semiconductor device of claim 1 , wherein input electrode of the logic component is in electric communication with the antiferromagnetic layer of the logic component, and wherein the ground electrode of the logic component is in electric communication with the free magnet of the logic component.

8. The semiconductor device of claim 1 , wherein the magnet isolation layer of the logic component and the magnet isolation layer of the bias component are composed of a material selected to have a high electrical resistivity.

Assignees

• Georgia Tech Res Inst

Inventors

• Pan Chenyun
• Dutta Sourav
• Naeemi Azad

Classifications

• H01L27/22

  Electricity · mapped topic

• H01F10/3218

  Exchange coupling of magnetic films via an antiferromagnetic interface (H01F10/3268 takes precedence) · CPC title

• H01F10/14

  containing iron or nickel ({H01F10/126} , H01F10/13, H01F10/16 take precedence) · CPC title

• H01L43/10

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic