Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress

Patent metadata

Field	Value
Publication number	US-2018233400-A1
Application number	US-201615554034-A
Country	US
Kind code	A1
Filing date	Feb 25, 2016
Priority date	Mar 3, 2015
Publication date	Aug 16, 2018
Grant date	—

Abstract

A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, a textured oxide, nitride, or oxynitride layer, a polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer. The multilayer structure is prepared in a manner that reduces wafer bow.

First claim

What is claimed is:

1 . A method of preparing a multilayer structure, the method comprising:
forming a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor oxynitride layer in interfacial contact with a front surface of a single crystal semiconductor handle substrate, the single crystal semiconductor handle substrate comprising two major, generally parallel surfaces, one of which is the front surface of the single crystal semiconductor handle substrate and the other of which is a back surface of the single crystal semiconductor handle substrate, a circumferential edge joining the front and back surfaces of the single crystal semiconductor handle substrate, a central plane between the front surface and the back surface of the single crystal semiconductor handle substrate, and a bulk region between the front and back surfaces of the single crystal semiconductor handle substrate, wherein the single crystal semiconductor handle substrate has a minimum bulk region resistivity of at least about 500 ohm-cm; annealing the single crystal semiconductor handle substrate comprising the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer in interfacial contact with the front surface thereof in an ambient atmosphere comprising a gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof; depositing a polycrystalline silicon layer on the semiconductor oxide layer, the semiconductor nitride layer, or the semiconductor oxynitride layer in interfacial contact with the front surface the single crystal semiconductor handle substrate, wherein the polycrystalline silicon layer is deposited by chemical vapor deposition; and bonding a dielectric layer on a front surface of a single crystal semiconductor donor substrate to the polycrystalline silicon layer of the single crystal semiconductor handle substrate to thereby form a bonded structure, wherein the single crystal semiconductor donor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor donor substrate and the other of which is a back surface of the semiconductor donor substrate, a circumferential edge joining the front and back surfaces of the semiconductor donor substrate, and a central plane between the front and back surfaces of the semiconductor donor substrate.

2 . The method of claim 1 wherein the single crystal semiconductor handle substrate comprises silicon, and the semiconductor oxide layer comprises silicon dioxide.

3 . The method of claim 1 wherein the single crystal semiconductor handle substrate comprises a silicon wafer sliced from a single crystal silicon ingot grown by the Czochralski method or the float zone method, and the semiconductor oxide comprises silicon dioxide.

4 . The method of claim 1 wherein the semiconductor oxide layer is deposited on the front surface of the single crystal semiconductor handle substrate, wherein the semiconductor oxide layer is formed by exposing the single crystal semiconductor handle substrate to an oxidizing medium selected from the group consisting of air, ozone, and an aqueous composition comprising an oxidizing agent.

5 . The method of claim 4 wherein the semiconductor oxide layer has a thickness between about 0.1 nanometers and about 25 nanometers.

6 . The method of claim 4 wherein the semiconductor oxide layer has a thickness between about 0.5 nanometers and about 5 nanometers.

7 . The method of claim 1 wherein the semiconductor nitride layer or the semiconductor oxynitride is deposited on the front surface of the single crystal semiconductor handle substrate.

8 . The method of claim 7 wherein the semiconductor nitride layer or the semiconductor oxynitride has a thickness between about 0.1 nanometers and about 25 nanometers.

9 . The method of claim 7 wherein the semiconductor nitride layer or the semiconductor oxynitride has a thickness between about 0.5 nanometers and about 5 nanometers.

10 . The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 500 Ohm-cm and about 100,000 Ohm-cm, or between about 1000 Ohm-cm and about 100,000 Ohm-cm.

11 . The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 1000 ohm cm and about 10,000 Ohm-cm, or between about 2000 Ohm cm and about 10,000 Ohm-cm.

12 . The method of claim 1 wherein the single crystal semiconductor handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm, or between about 3000 Ohm cm and about 5,000 Ohm-cm.

13 . The method of claim 1 wherein the single crystal semiconductor handle substrate comprises the semiconductor oxide layer on the front surface thereof, which is annealed in the ambient atmosphere comprising the gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof prior to deposition of the polycrystalline silicon layer.

14 . The method of claim 13 wherein the single crystal semiconductor handle substrate comprises the semiconductor oxide layer on the front surface thereof, which is annealed in the ambient atmosphere comprising a gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof at a temperature greater than about 850° C.

15 . The method of claim 13 wherein the single crystal semiconductor handle substrate comprises the semiconductor oxide layer on the front surface thereof, which is annealed in the ambient atmosphere comprising the gas selected from the group consisting of hydrogen, hydrogen chloride, chlorine, and any combination thereof at a temperature between about 850° C. and about 1000° C.

16 . The method of claim 13 wherein the anneal of the single crystal semiconductor handle substrate comprising the semiconductor oxide layer forms a textured semiconductor oxide layer comprising holes having sizes between about 5 nanometers and about 1000 nanometers.

17 . The method of claim 1 the polycrystalline silicon layer is deposited from a deposition ambient atmosphere comprising a silicon precursor selected from the group consisting of silane, trichlorosilane, dichlorosilane, and any combination thereof at a deposition rate of at least about 0.1 micrometer/minute.

18 . The method of claim 1 the polycrystalline silicon layer is deposited from a deposition ambient atmosphere comprising a silicon precursor selected from the group consisting of silane, trichlorosilane, dichlorosilane, and any combination thereof at a deposition rate between about 0.1 micrometer/minute to about 2 micrometers/minute.

19 . The method of claim 1 wherein deposition by chemical vapor deposition of the polycrystalline silicon layer is interrupted after deposition of a polycrystalline silicon seed layer, and further wherein the polycrystalline seed layer is annealed at a temperature greater than about 1000° C.

20 . The method of claim 19 wherein the polycrystalline silicon seed layer has a thickness of less than 3 micrometers.

21 . The method of claim 19 wherein deposition by chemical vapor deposition of the polycrystalline silicon layer is resumed after cooling the single crystal semiconductor handle substrate to a temperature between about 850° C. and about 1000° C.

22 . The method of claim 1 wherein deposition by chemical vapor deposition of the polycrystalline s

Assignees

• Sunedison Semiconductor Ltd Uen201334164H

Inventors

• Wang Gang
• Libbert Jeffrey L
• Thomas Shawn George
• Peidous Igor

Classifications

• H10P90/1914

  using bonding · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3256

  Microstructure · CPC title

• H10P14/3238

  being insulating materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title